Presentation is loading. Please wait.

Presentation is loading. Please wait.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 426 - VLSI System Design Lecture 3 - Verilog Delay.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 426 - VLSI System Design Lecture 3 - Verilog Delay."— Presentation transcript:

1 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 426 - VLSI System Design Lecture 3 - Verilog Delay Modeling February 3, 2003

2 2/3/03ECE 426 - Lecture 32 Announcements  Reading  Wolf: 8.1-8.3

3 2/3/03ECE 426 - Lecture 33 Where we are...  Last Time:  Verilog Review  Event-Driven Simulation  Today:  Timing and Delay in Event-Driven Simulation  Verilog Delay Constructs  initial blocks  Tasks and Functions  Discuss Lab 1

4 2/3/03ECE 426 - Lecture 34 Verilog and Event-Driven Simulation  Key idea: model circuit operation as sequence of events that take place at specific times  Input events - when input changes  Output events - response to input events (only generated when output changes) A B C A B C delay=4 input event output event

5 2/3/03ECE 426 - Lecture 35 Event-Driven Simulation  Example: Modeling and AND Gate  Input events: changes on A, B input net  Output events: changes on C output net after delay A B C A B C t=5 A=1 t=17 B=1 t=33 B=0 t=29 C=1 delay=12 t=45 C=0 Input Events Output Events

6 2/3/03ECE 426 - Lecture 36 Event-Driven Simulation (cont'd)  Processing Events - Data Structures  Event - specifies time event will occur net where signal will change new value of net  Event Queue - data structure that sorts events by time front of queue - earliest event back of queue - latest event also called a timing wheel

7 2/3/03ECE 426 - Lecture 37 Event-Driven Simulation - Algorithm  Processing Events - Simulation Algorithm initialization: set all nets & regs to ‘x’ while (event queue not empty) { current_event = "earliest" event in queue; current_time = current_event.time; current_event.net.value = current_event.value; for (each module input connected to net) { evaluate(module) if output of module changes { create new event to represent output change add new event to queue } } }

8 2/3/03ECE 426 - Lecture 38 Verilog Simulation Model  assign statement  executes when event changes any input  produces output event when output values changes  always block  executes when event changes variable in sensitivity list  produces output events when outputs change assign y = ~a; always @(a or b) x = a ^ b;

9 2/3/03ECE 426 - Lecture 39 Delays in Event-Driven Simulation  Two kinds of delays supported:  Inertial delays - reflects limited response time in real gates  Transport delays - try to model delay through a wire

10 2/3/03ECE 426 - Lecture 310 Inertial Delays  What happens here? A B C A B C delay=t d t1t1 t2t2 tdtd t 2 - t 1 > t d A B C A B C delay=t d t1t1 t2t2 tdtd t 2 - t 1 < t d Event-driven model: Narrow Pulse Real gate: No change (why?)

11 2/3/03ECE 426 - Lecture 311 Inertial Delays in Event-Driven Simulators  Each signal change is scheduled in event queue  When scheduling, compare to most recent change to calculate “pulse width”  If (pulse_width < prop_delay) deschedule both events 3 Delay = 2 5 4 6 De-scheduled Events 3 5911

12 2/3/03ECE 426 - Lecture 312 Transport Delays  What happens here? A C delay=t d Long Wire B A B tdtd Change propagated independent of pulse width

13 2/3/03ECE 426 - Lecture 313 Modeling Delays in Verilog  Delays in Structural Verilog  Gate primitives: inertial delays and #5 g1(o1, a, b);  Net delays (transport) wire #5 w1;  More complex modules: specify  Delays in Behavioral Verilog  assign statements assign #10 a = x & y;  always & initial blocks blocking delay #10 a = x +y; interassignment delay a = #10 x + y;

14 2/3/03ECE 426 - Lecture 314 Structural Delay - Gate Primitives and G1 (y1, a, b); and #5 G2 (y2, a, b); and #(7,5) G3 (y3, a, b); and #(6:7:8,4:5:6) G4 (y4, a, b); buf_if1 #(6,5,2) B1 (y5, a, enb); // 3-state buf rising delayfalling delaysingle delay value rising delay min : typ : max falling delay min : typ : max no delay value (delay = 0)rising delayturnoff delay falling delay

15 2/3/03ECE 426 - Lecture 315 Structural Delay - specify block  Used to specify arbitrary input, output delays module norf201(O, A1, B1); output O; input A1, B1; nor(O, A1, B1); specify (A1, B1 *> O) = (0.2:0.3:0.8, 0.2:0.8:0.5); endspecify endmodule specifies delay paths rising delay min : typ : max falling delay min : typ : max Example Source: M Ciletti, Modeling, Synthesis, and Rapid Prototyping with Verilog HDL, Prentice-Hall, 1999

16 2/3/03ECE 426 - Lecture 316 More about specify blocks  Like all other delays, not supported by synthesis  More features available  Edge-based delays  Parameterized delays ( specparam )

17 2/3/03ECE 426 - Lecture 317 Delay in assign statements  Delay specified as in structural specifications assign #5 y1 = a & b; assign (#4,#5,$6) y2 = a & b;  Specifies inertial delay

18 2/3/03ECE 426 - Lecture 318 Delays in Behavioral Verilog - Blocking Delay  Delay control operator - #n  Simulation effect: suspends simulation for n time units  Example: clock generator always begin clk = 0; #50 clk = 1; #50 ; end null statement (suspends simulation 50 time units)

19 2/3/03ECE 426 - Lecture 319 Delays in Behavioral Verilog - Interassignment Delay  Key idea: unlike blocking delay, RHS is evaluated before delay  With blocking assignments: a = #5 b + c; d = a;  With nonblocking assignments: a <= #5 b + c; d = a; b + c evaluated; change in a scheduled delayed until 5 time units elapse b + c evaluated; change in a scheduled executes immediately; gets OLD value of a!

20 2/3/03ECE 426 - Lecture 320 Representing Time in Verilog  Verilog uses “dimensionless” time units  Mapping time units to “real” time: `timescale `timescale /  Examples `timescale 1ns / 1ps `timescale 10ns / 100ps  Each module can have a different timescale (but this is not necessarily a good idea!) Time Units of # Delay Values Minimum step time used by simulator

21 2/3/03ECE 426 - Lecture 321 Simulation Time in Verilog: # and `timescale  `timescale controls simulation time `timescale time_unit time_precision `timescale 1ns 100ps  # operator specifies delay in terms of time units `timescale 1ns 100ps #5 // delays 5*1ns = 5ns; // rounds times to 100ps `timescale 4ns 1ns #3 // delays 3*4ns = 12ns // rounds times to 1ns

22 2/3/03ECE 426 - Lecture 322 What happens when no delays are specified?  Each output event has a “delta” delay  Events processed in order of scheduling

23 2/3/03ECE 426 - Lecture 323 More about Verilog  initial blocks  functions  tasks  forks & joins

24 2/3/03ECE 426 - Lecture 324 initial statements  Specify code to be executed on simulation startup initial sequential_statement  Not supported in synthesis - tell synthesis to ignore using “pragmas”  Very useful in testbenches! initial // synopsys translate_off begin … code to generate input stimulus end // synopsys translate_on

25 2/3/03ECE 426 - Lecture 325 Verilog functions  Function Declaration: function [ range_or_type ] fname; input_declarations statement endfunction  Return value: function body must assign: fname = expression;  Function call: fname ( expression,… )

26 2/3/03ECE 426 - Lecture 326 Verilog Functions (cont'd)  Function characteristics:  returns a single value (default: 1 bit)  can have multiple input arguments (must have at least one)  can access signals in enclosing module  can call other functions, but not tasks  cannot call itself (no recursion)  executes in zero simulation time (no timing ops allowed)  Synthesized as combinational logic (if proper subset is used)

27 2/3/03ECE 426 - Lecture 327 Verilog Functions (cont'd)  Function examples: function calc_parity; input [31:0] val; begin calc_parity = ^val; end endfunction function [15:0] average; input [15:0] a, b, c, d; begin average = (a + b + c + d) >> 2; end endfunction;

28 2/3/03ECE 426 - Lecture 328 Verilog Tasks  Similar to procedures in VHDL  Multiple input, output, and inout arguments  No explicit return value (use output arguments instead)  No recursion allowed  Can "enable" (call) other tasks and functions  May contain delay, event, and timing control statements (but not in synthesis)

29 2/3/03ECE 426 - Lecture 329 Verilog Tasks (cont'd)  Task example: task ReverseByte; input [7:0] a; output [7:0] ra; integer j; begin for (j = 7; j >=0; j=j-1) ra[j] = a[7-j]; end endtask // Adapted from "Verilog HDL Synthesis: A Practical // Primer", by J. Bhasker

30 2/3/03ECE 426 - Lecture 330 System Tasks and Functions  Tasks and functions defined for simulator control  All named starting with "$" (e.g., $monitor)  Standard - same for every simulator (almost)  See Verilog Quick Reference Card, Section 8 for full list of system tasks  Example system task: $display $display("format-string", expr1, …, exprn); format-string - regular ASCII mixed with formatting characters %d - decimal, %b - binary, %h - hex, %t - time, etc. other arguments: any expression, including wire s and reg s $display("Error at time %t: value is %h, expected %h", $time, actual_value, expected_value);

31 2/3/03ECE 426 - Lecture 331 Some useful System Tasks  $time - return current simulation time  $monitor - print message when values change $monitor("cs=%b, ns=%b", cs, ns)  Simulation control tasks  $stop - interrupt simulation  $finish - terminate simulation  Extensive file I/O also available

32 2/3/03ECE 426 - Lecture 332 Parallel Blocks - fork / join  Allows concurrent execution in a sequential block  Not supported in synthesis  Basic structure fork parallel-statement1; parallel-statement2; … join

33 2/3/03ECE 426 - Lecture 333 Lab 1 Overview:  Key idea: registered outputs in FSMs can be useful for storage  Example: SAR FSM  Build a FSM as a single always block  Use registered outputs for estimate E[3:0]

34 2/3/03ECE 426 - Lecture 334 Lab 1 Code Skeleton module SAR_REG(clk, reset, start, E) input clk, reset, start; output E[3:0]; reg E[3:0]; parameter S0=2’d0, S1=2’d1, …; reg cs[1:0]; always @(posedge clk) begin if (reset) …. ; case (cs) S0: if (start) begin E <= 4’b1000; cs <= S1; end else cs <= S0;

35 2/3/03ECE 426 - Lecture 335 Lab 1 Tasks  Re-Code FSM using Registered Outputs  Simulate w/ Verilogger to check outputs  Synthesize & compare to original design from last semester

36 2/3/03ECE 426 - Lecture 336 Coming Up:  Verilog coding styles  Behavioral Modeling  Testbenches and Verification

37 2/3/03ECE 426 - Lecture 337 Verilog Stuff we Won’t Talk about Much  Procedural continuous assignment  Assign / desassign as procedural statements  Not synthesizeable  User-Defined Primitives (UDPs)

38 2/3/03ECE 426 - Lecture 338 More about Verilog FSMs  Many ways to describe  Explicit Style 1 State register - clocked always block Next-state Logic - combinational always block Output logic - combinational always block (or assign)  Explicit Style 2 Next-state logic AND state register: clocked always block Output logic - combinational always block (or assign)

39 2/3/03ECE 426 - Lecture 339 Lab 1 - FSM Coding  Re-code SAR as  Explicit FSM w/ registered outputs  Implicit FSM

40 2/3/03ECE 426 - Lecture 340 System Design Issues  ASM Diagrams  Synchronization & Metastability  Handshaking  Working with Multiple Clocks

Download ppt "Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 426 - VLSI System Design Lecture 3 - Verilog Delay."

Similar presentations

VERILOG: Synthesis - Combinational Logic Combination logic function can be expressed as: logic_output(t) = f(logic_inputs(t)) Rules Avoid technology dependent.

VERILOG: Synthesis - Combinational Logic Combination logic function can be expressed as: logic_output(t) = f(logic_inputs(t)) Rules Avoid technology dependent.
Verilog HDL -Introduction

Verilog HDL -Introduction
CS 3850 Lecture 6 Tasks and Functions. 6.1 Tasks and Functions Tasks are like procedures in other programming languages. e. g., tasks may have zero or.

CS 3850 Lecture 6 Tasks and Functions. 6.1 Tasks and Functions Tasks are like procedures in other programming languages. e. g., tasks may have zero or.
Simulation executable (simv)

Simulation executable (simv)
Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.

Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.
ECE 551 Digital Design And Synthesis

ECE 551 Digital Design And Synthesis
Synchronous Sequential Logic

Synchronous Sequential Logic
ELEN 468 Lecture 61 ELEN 468 Advanced Logic Design Lecture 6 Delay Models.

ELEN 468 Lecture 61 ELEN 468 Advanced Logic Design Lecture 6 Delay Models.
Combinational Logic.

Combinational Logic.
Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 07: Verilog (3/3) Prof. Sherief Reda Division of.

Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 07: Verilog (3/3) Prof. Sherief Reda Division of.
Verilog Intro: Part 1.

Verilog Intro: Part 1.
Hardware Description Language (HDL)

Hardware Description Language (HDL)
2/9/20031 ECE 551: Digital System Design & Synthesis Lecture Set 4 4.1: Verilog – Procedural Assignments &Scheduling Semantics 4.2: Verilog – More Behavioral.

2/9/20031 ECE 551: Digital System Design & Synthesis Lecture Set 4 4.1: Verilog – Procedural Assignments &Scheduling Semantics 4.2: Verilog – More Behavioral.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 491 - Senior Design I Lecture 4 - Sequential Design.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Senior Design I Lecture 4 - Sequential Design.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 491 - Senior Design I Lecture 5 - Coding Guidelines;

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Senior Design I Lecture 5 - Coding Guidelines;
Digital System Design by Verilog University of Maryland ENEE408C.

Digital System Design by Verilog University of Maryland ENEE408C.
ENEE 408C Lab Capstone Project: Digital System Design Verilog Tutorial Class Web Site:

ENEE 408C Lab Capstone Project: Digital System Design Verilog Tutorial Class Web Site:
Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.

Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.
ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II.

ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II.
Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.

Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.

Similar presentations

Ads by Google