1. Ki-Hyung Kim Division of Information and Computer Eng. Ajou University
Processor/Interface
Ki-Hyung Kim
Division of Information and Computer Eng.
Ajou University

2. 임베디드 시스템 구조 Coordination of many levels of abstraction Software
I/O system
Processor
Compiler
Operating
System
(Windows 98)
Application (Netscape)
Digital Design
Circuit Design
Instruction Set
Architecture
Datapath & Control
transistors
Memory
Hardware
Software
Assembler
Coordination of many levels of abstraction

3. 임베디드 시스템 H/W 구조 임베디드 시스템 구성 임베디드 H/W 프로세서/컨트롤러
메모리, I/O 인터페이스, 네트워크 인터페이스
Processor
(active)
Embedded System
Control
(“brain”)
Datapath
(“brawn”)
Memory
(passive)
(where
programs,
data
live when
running)
Devices
Input
Output

4. 임베디드 H/W 구성요소 임베디드 프로세서/컨트롤러 대부분의 프로세서가 임베디드 시스템용으로 사용
많은 종류의 마이크로프로세서/컨트롤러들 중에서 응용에 최적인 제품을 찾아내는 것이 설계에서 매우 어렵고 중요한 작업
Embedded Computers
80%
8.5B Parts per Year
Robots 6%
Vehicles 12%
Direct 2%
Source: DARPA/Intel (Tennenhouse)
대부분의 프로세서가
임베디드용으로 사용됨

5. 임베디드 H/W 구성요소(2) 메모리 버스 주변 장치 기타 ROM/RAM Timer/Counter Interrupt DMA
고속/대용량화
FLASH 메모리의 사용증가.
CACHE/Virtual Memory 효용성 버스
주변 장치
Timer/Counter
Interrupt
DMA 기타

6. 임베디드 프로세서 Computation tasks를 주로 담당 다양한 주변 인터페이스를 포함하는 SoC 형태로 발전
처리속도, 전력 소비, 가격 뿐만 아니라 개발환경과의 연관 관계가 매우 중요
제어 장치(control unit)와 연산부(data-path)로 구성
프로세서 선택 중요
ARM, PPC, MIPS, i386, Alpha, Sparc, m68k
SH, CRIS, IA64, PARISC 등
MSP430, Atmega128 (AVR), i8051
본 강좌에서는 하나의 예로 ARM core를 기반으로 설명

7. 프로세서 기본 구조 Control unit 과 data-path로 구성 특징 General data-path
Control unit doesn’t store the algorithm – the algorithm is “programmed” into the memory
Processor
Control unit
Data-path
ALU
Registers IR PC
Controller
Memory
I/O
Control
/Status

8. Data-path 동작 ... Load ALU Store Read memory location into register
Arithmetic/logical operation
Store
Write register into memory location
Processor
Control unit
Datapath
ALU
Registers IR PC
Controller
Memory
I/O
Control
/Status 10
... +1 11

9. 제어 장치(Control Unit)
Control unit: configures the data-path operations
Sequence of desired operations (“instructions”) stored in memory – “program”
Instruction cycle – broken into several sub-operations, each one clock cycle:
Fetch: Get next instruction into IR
Decode: Determine what the instruction means
Fetch operands: Move data from memory to data-path register
Execute: Move data through the ALU
Store results: Write data from register to memory
Processor
Control unit
Datapath
ALU
Registers IR PC
Controller
Memory
I/O
Control
/Status 10
...
load R0, M[500]
500
501
100
inc R1, R0
101
store M[501], R1
102 R0 R1

10. CISC and RISC 구조 CISC - Complex Instruction Set Computer
관련된 연산을 수행하는 수많은 명령을 가짐
CISC code is compact
Can be many clock cycles per instruction
Large silicon area > Higher cost per die
RISC - Reduced Instruction Set Computer
More modern architecture
One instruction executed per clock cycle > Very fast
RISC CPU cores tend to be small
Typical dynamic instruction usage
Data movement, Control flow, Arithmetic operations, Comparisons, Logical operations 이 99%를 차지함
Risc의 가능성을 보여줌(?)

11. BUS
A Bus Is:
shared communication link
single set of wires used to connect multiple subsystems
Data Bus, Address Bus, Control Bus
Input/Output Bus (eg. PCI) – 표준화되어야됨.
System Bus (local bus)- 고속이 목표, Processor에 의존적  chipset
A Bus is also a fundamental tool for composing large, complex systems
systematic means of abstraction
Control
Datapath
Memory
Processor
Input
Output

12. 폰 노이만 아키텍처
memory
CPU
200
address
data IR
ADD r5,r1,r3
Embedded System

15. 하버드 아키텍처 address data memory data CPU PC program memory
Harvard can’t use self-modifying code.
Harvard allows two simultaneous memory fetches.
Most DSP use Harvard architecture for streaming data:
greater memory bandwidth;
more predictable bandwidth.
CPU PC
data memory
program memory
address
data

16. Pipeline in RISC T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3
T1: instruction fetch
T2: decode
T3: Execution (Load from Memory)
T4: Write to Memory (or Register) T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5

17. MIPS
MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a RISC microprocessor architecture developed by MIPS Technologies. By the late 1990s it was estimated that one in three RISC chips produced were MIPS-based designs.

18. Pipeline in CISC T1 T2 T3 T4 T5 T6 T7 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6
파이프라인의 개수와 길이가 가변
 파이프라인을 만들기 어렵다.
 파이프라인의 각 스텝을 길이를 최소화하기어렵다. T1 T2 T3 T4 T5 T6 T7 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T1 T2 T3 T4 T5

19. Simplified Harvard Architecture of ARM
TCM: Tightly Coupled Memory ( Used for Realtime programs)

20. Dataflow Architecture
Program counter 가 없다.
다음에 실행시킬 인스트럭션을 지정하는 기능이 없다.
다음에 실행시킬 인스트럭션은 어떤 인스트럭션이든 필요한 데이터가 준비되면 바로 실행된다. (병렬로)
메모리(실행될 instruction들)
Add M1 + M2  M3
ALU
ALU
ALU
ALU

21. Dataflow Architecture 2
Dataflow architecture is a computer architecture that directly contrasts the traditional von Neumann architecture or control flow architecture.
Dataflow architectures do not have a program counter or (at least conceptually) the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions.

22. 메모리 - ROM Read-Only Memory (ROM) Non-volatile storage
ROM, PROM, EPROM, EEPROM
OT-PROM (one time programmable)
Mask ROM
Fuse ROM
PROM(programmable)
EPROM
EEPROM
Word Line
Bit Line
Mask ROM
Fuse ROM
EPROM
EEPROM
Flash Memory
Floating
gate
Brief tour of computer memory.
Storing data and retaining program state were early and fundamental problems in computer development.
Tubes arranged as flip-flops very expensive—waste of active devices.
Early attempts included delay line approaches (mechanical spring, mercury pool), phosphor state, magnetic domains (core, drums, tape, etc.)
Semiconductor memory only became cheap enough around 1970, and was Intel’s first product.

34. Flash Memory NOR NAND XIP
In computer science, execute in place (XIP) is a method of executing programs directly from long term storage rather than copying it into RAM. It is an extension of using shared memory to reduce the total amount of memory required.

35. 메모리 - RAM Random Access Memory 전원이 인가되는 상태에서만 데이터를 유지
Two main types: Static RAM (SRAM) and Dynamic RAM (DRAM)
비트가 저장되는 방법 상에 차이점이 존재
Static RAM
Fast (active drive)
Less dense (4-6 transistors/bit)
Stable (holds value as long as power applied)
Dynamic RAM
Slower
High density (1 transistor/bit)
Unstable (needs refresh)
Other types: SDRAM, Video RAM, FERAM
Brief tour of computer memory.
Storing data and retaining program state were early and fundamental problems in computer development.
Tubes arranged as flip-flops very expensive—waste of active devices.
Early attempts included delay line approaches (mechanical spring, mercury pool), phosphor state, magnetic domains (core, drums, tape, etc.)
Semiconductor memory only became cheap enough around 1970, and was Intel’s first product.

36. Inverter with CMOS

37. NAND with CMOS

38. NOR in NMOS

39. SRAM

40. DRAM

41. SDRAM
SDRAM refers to synchronous dynamic random access memory, a term that is used to describe dynamic random access memory that has a synchronous interface. Traditionally, dynamic random access memory (DRAM) has an asynchronous interface which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus.

42. 성능(Performance) -- ThroughputRD
값이출력
Latency (지연시간)
성능(Performance) -- Throughput

43. RAM의 기본 구조 Word Lines Bit Cell Bit Lines High Sense Amplifier Low Data
Address
High
Low
Data
Brief tour of computer memory.
Storing data and retaining program state were early and fundamental problems in computer development.
Tubes arranged as flip-flops very expensive—waste of active devices.
Early attempts included delay line approaches (mechanical spring, mercury pool), phosphor state, magnetic domains (core, drums, tape, etc.)
Semiconductor memory only became cheap enough around 1970, and was Intel’s first product.

44. Typical 16 Mb DRAM (4M x 4)

45. Static RAM (SRAM) 구조 및 access
Word
Line
Bit
!Bit
Read: Drive word line, sense value on bit lines
Write: Drive word line, drive new value (strongly) on bit lines CE
Addr
Data
Read
Write
Accessing a Static RAM
Note: CE signal is often active-low as opposed to how shown here. SRAMs also generally have a write enable signal
Where is the data physically stored? What energy form?

46. Dynamic RAM (DRAM)
Read: Drive word line, sense value on bit line (destroys saved value)
Write: Drive word line, drive new value on bit line.
Word Line
Bit Line
RAS
Dynamic RAM Timing (Read)
Control signals are often active-low
CAS
Addr
Process modifications to enhance capacitor storage capacity.

47. Other RAM Types Video RAM SDRAM Flash RAM FERAM Nanotech RAMs
Optimized for high-speed regular accesses to frame buffer
SDRAM
Uses clocked organization to pipeline for speed
Flash RAM
Non-volatile (holds data without power)
FERAM
Uses magnetic technology (similar to hard disk) to store data
Holds value when power off
Capacity, access time similar to RAM (hard disks take ms)
Nanotech RAMs
Molecular electronics, carbon nanotubes
Nowhere near ready for prime time

48. Frame Buffer in Graphic Card
Video DRAM
VRAM is a dual-ported variant of DRAM which was once commonly used to store the frame-buffer in some graphics adaptors.
Dual-ported RAM (DPRAM) is a type of Random Access Memory that allows multiple reads or writes to occur at the same time, or nearly the same time, unlike single-ported RAM which only allows one access at a time.
Video RAM or VRAM is a common form of dual-ported dynamic RAM mostly used for video memory, allowing the CPU to draw the image at the same time the video hardware is reading it out to the screen.
VRAM
Frame Buffer in Graphic Card
CPU
DVI

49. Flash Memory
1. NOR 형 • cell 이 병렬로 배치되어 random access 가 가능하고 byte 단위로 프로그래밍 가능. • 읽기 속도가 NAND 형보다 빠르지만, 쓰기/지우기 속도는 느리다. • 각 cell 마다 비트선의 접촉전극이 필요하여 NAND 형에 비해 cell 당 면적이 많이 필요하고 비싸다. • 읽기 속도가 빠르므로 코드 저장용(주로 디바이스의 OS 부팅용)으로 사용한다 NAND 형 • cell 이 직렬로 배치되어 page/block 단위로 읽고 쓰기 가능. • random access 가 불가능하여 읽기 속도가 NOR 형에 비해서 느리지만, 쓰기/지우기 속도는 빠름. • 집적 밀도가 높다 • 대용량화가 가능하므로 데이터 저장용(디지털 카메라, MP3 등)으로 사용한다. 요약 NOR 형은 대용량화가 어렵고 NAND 형은 읽기 속도가 느리다는 단점이 있다

50. Cache Systems SRAM  DRAM CPU Cache Main Memory Main Memory 10MHz
Data object transfer
Block transfer
400MHz
Main Memory 10MHz
Bus 66MHz

51. Why Memory Hierachy?

52. Cache Mechanism (1)

53. Cache Address Mapping

54. 512 byte 캐쉬의 라인? 4byte 4byte 4byte 4byte 4byte Cache Block
1block = 4 byte
4byte
128블록
4byte
4byte
4byte
4byte

55. 512 byte 캐쉬의 라인? 4byte 4byte 4byte 4byte 4byte 4byte 4byte 4byte 4byte
1block = 16 byte (4word)
4byte
4byte
4byte
4byte
32블록
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte
4byte

56. 0번 라인 캐쉬 엔트리에 들어올수 있는 블록의 태그는?
Cache entry 가 8개이면?  1way cache (direct mapped cache)
Tag=0
Tag=1
0번 라인 캐쉬 엔트리에 들어올수 있는 블록의 태그는?
캐쉬가 8라인이면 (0, 8, 16, 24,…
캐쉬가 256라인이면 (0, 256, 512,)

57. Cache entry 가 8개이면?  2 way set-associative cache
way 1, way 2
Set 0
Set 1
Set 2
Set 3
Tag: index가 set 안에 있나 없나?
Set: set ID

58. Cache entry 가 8개이면?  4 way cache

59. Cache entry 가 8개이면?  n way set associative cache (n=8, s=1) – Fully associative cache

60. Direct Mapped

61. Direct Mapping Cache Organization

62. Direct Mapping Example

63. Direct Mapping pros & cons
Simple
Inexpensive
Fixed location for given block
If a program accesses 2 blocks that map to the same line repeatedly, cache misses are very high

64. Direct Mapping Cache Line Table
Cache line Main Memory blocks held
0 0, m, 2m, 3m…2s-m
1 1,m+1, 2m+1…2s-m+1
m-1 m-1, 2m-1,3m-1…2s-1

65. 2 Way Set Associative

66. Set Associative Cache 2 S0 S1 S2
A0, A1

67. Set Associative Mapping
Cache is divided into a number of sets
Each set contains a number of lines
A given block maps to any line in a given set
e.g. Block B can be in any line of set i
e.g. 2 lines per set
2 way associative mapping
A given block can be in one of 2 lines in only one set

68. Set Associative Mapping Example
13 bit set number
Block number in main memory is modulo 213
000000, 00A000, 00B000, 00C000 … map to same set

69. Two Way Set Associative Cache Organization

70. Set Associative Mapping Address Structure
Word
2 bit
Tag 9 bit
Set 13 bit
Use set field to determine cache set to look in
Compare tag field to see if we have a hit
e.g
Address Tag Data Set number
1FF 7FFC 1FF FFF
001 7FFC FFF

71. Two Way Set Associative Mapping Example

72. Fully Associative Cache

73. Associative Mapping
A main memory block can load into any line of cache
Memory address is interpreted as tag and word
Tag uniquely identifies block of memory
Every line’s tag is examined for a match
Cache searching gets expensive

74. Fully Associative Cache Organization

75. Associative Mapping Example

76. Associative Mapping Address Structure
Word
2 bit
Tag 22 bit
22 bit tag stored with each 32 bit block of data
Compare tag field with tag entry in cache to check for hit
Least significant 2 bits of address identify which 16 bit word is required from 32 bit data block
e.g.
Address Tag Data Cache line
FFFFFC FFFFFC FFF

77. Replacement Algorithms (1) Direct mapping
No choice
Each block only maps to one line
Replace that line

78. Replacement Algorithms (2) Associative & Set Associative
Hardware implemented algorithm (speed)
Least Recently used (LRU)
e.g. in 2 way set associative
Which of the 2 block is lru?
First in first out (FIFO)
replace block that has been in cache longest
Least frequently used
replace block which has had fewest hits
Random

79. Locality of Reference LRU (timestamp(access) 가 필요)
way 1, way 2
frequency
Set 0
Set 1
Set 2
Set 3
Locality of Reference
LRU (timestamp(access) 가 필요)
LFU (frequency(access)가 필요)
FIFO (timestamp(로딩된 시간))

80. Access pattern 0,1,0,0,1,0,0,1 Frequency: 0=5, 1=3
timestamp 1
Set 0
Set 1
Set 2
Set 3
frequency
Access pattern
0,1,0,0,1,0,0,1
Frequency: 0=5, 1=3
Access timestamp: 1이 최근
Loading timestamp: 0 이old

81. Write Policy
Must not overwrite a cache block unless main memory is up to date
Multiple CPUs may have individual caches
 cache coherency (일관성=여러 개의 캐쉬의 데이터와 메인메모리의 데이터가 같아야 함)
I/O may address main memory directly

82. Write through All writes go to main memory as well as cache
Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date
Lots of traffic
Slows down writes
Remember bogus write through caches!

83. Write back Updates initially made in cache only
Update bit for cache slot is set when update occurs
If block is to be replaced, write to main memory only if update bit is set
Other caches get out of sync
I/O must access main memory through cache
N.B. 15% of memory references are writes

84. The Memory System Embedded systems and applications Simple blocks
The memory system requirements: vary considerably
Simple blocks
Multiple types of memory
Caches
Write buffers
Virtual memory

85. Memory management units
Memory management unit (MMU) translates addresses:
Protection checks
main
memory
logical
address
memory
management
unit
physical
address
CPU

86. Memory management tasks
Allows programs to move in physical memory during execution
Allows virtual memory:
memory images kept in secondary storage;
images returned to main memory on demand during execution
Page fault: request for location not resident in memory

87. Address translation
Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses
Two basic schemes:
segmented
paged
Segmentation and paging can be combined (x86)

88. 메모리 단편화(Fragmentation)P1 P5 P2 P2 P3
단편화
(fragmentation) P3 P3

89. 압축(compaction) P2 P5 P2 P3 P3

90. Segments and pages page 1 Size가 고정 page 2 segment 1 memory Size가 가변

91. Code and data segment (section)
#include <stdio.h>
int a,b,c=3;
static int k=2;
void main(void) {
{int d=5;
int e=c; int d=f;
e=add(3,5);d=add(3,5)}
int *p = (int*) malloc(int); }
int add(int y, int z)
{ int d=7;
static int f++=7;
return y+z+f;
Text (code)
Data
BSS (Block Started by Symbol)
또는 Block Static Storage
Heap
Stack

92. Heap과 Stack
SP(Stack Pointer)

93. Code and data segment (section)
Text (code)
COFF 또는 ELF Header
Loading
Text (code)
LD(.so)
Data
Data
BSS (Block Started by Symbol)
또는 Block Static Storage
Symbol table
Heap
Stack

94. Storage class and Scope
Static vs Volatile
Static vs Dynamic
Static vs External (In C and C++) extern
Static vs Instance (Class variable in C++ and Java)
Local vs Global
Fixed (size) data vs Variable (size) data
Variable(dynamic) 메모리는 단편화의 위험이 있다.

96. Segment address translation
segment base address
logical address +
segment lower bound
range
error
range
check
segment upper bound
physical address

97. Page address translation
offset
page i base
concatenate
page
offset

98. Page table organizations
tree
page
descriptor
flat
page descriptor

99. Caching address translations
Large translation tables require main memory access
TLB: cache for address translation
Typically small

100. ARM Memory Management Unit

101. ARM Memory Management System control coprocessor(CP15) Registers
Write Buffers
Caches
Registers
Up to 16 primary registers
Physical registers in CP15 more than 16
Register access instructions
MCR (ARM to CP15)
MRC (CP15 to ARM)

102. Cached MMU memory system

103. Page table size for 4-KB pages : 220 X 4 bytes = 4 MB
ARM Memory Management
MMU can be enabled and disabled
Memory region types:
section: 1 Mbytes block
large page: 64 Kbytes
small page: 4 Kbytes
tiny Page: 1 Kbytes
Two-level translation scheme (why?)
First-level table
Second-level table
Page table size for 4-KB pages : 220 X 4 bytes = 4 MB

104. ARM address translation
Translation table
base register
1st index
2nd index
offset
1st level table
descriptor
concatenate
2nd level table
descriptor
physical address

105. First-level descriptors
AP: access permission
C,B: cachability and bufferability

106. Section descriptor and translating section references
CP reg 2:
16 KB boundary
4K Entries
1 MB block (section)
Max: 16KB

107. Coarse Page table descriptor
4 K entries
256 entries
Max: 16KB
Max: 1KB

108. Fine page table descriptor
1 K entries
Max: 4 KB

109. Second-level descriptor

110. Translating large page references

111. Access permissions
System (S) and ROM (R) in CP15 register 1

112. TLB functions Invalidate instruction TLB
Invalidate instruction single entry
Invalidate entire data TLB
Invalidate data single entry
TLB lockdown

113. PC Bus Architecture
The northbridge, also known as the memory controller hub (MCH) in Intel systems (AMD, VIA, SiS and others usually use 'northbridge'), is traditionally one of the two chips in the core logic chipset on a PC motherboard
The Southbridge, also known as the I/O Controller Hub (ICH) in Intel systems (AMD, VIA, SiS and others usually use 'southbridge'), is a chip that implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture.

114. I/O devices Usually includes some non-digital component
Typical digital interface to CPU:
CPU
status
reg
data
mechanism

115. I/O addressing
A microprocessor communicates with other devices using some of its pins
Port-based I/O (parallel I/O)
Processor has one or more N-bit ports
Processor’s software reads and writes a port just like a register
E.g., P0 = 0xFF; v = P1; -- P0 and P1 are 8-bit ports
Bus-based I/O
Processor has address, data and control ports that form a single bus
Communication protocol is built into the processor
A single instruction carries out the read or write protocol on the bus

116. Bus-based I/O 프로세서는 동일한 버스를 사용해서 메모리나 주변장치와 통신 Memory-mapped I/O
Peripheral registers occupy addresses in same address space as memory
e.g., Bus has 16-bit address
lower 32K addresses may correspond to memory
upper 32k addresses may correspond to peripherals
Standard I/O (I/O-mapped I/O)
Additional pin (M/IO) on bus indicates whether a memory or peripheral access
all 64K addresses correspond to memory when M/IO set to 0
all 64K addresses correspond to peripherals when M/IO set to 1

117. Memory-mapped vs. Standard I/O
Memory-mapped I/O
다른 특별한 명령이 요구되지 않음
Assembly instructions involving memory like MOV and ADD work with peripherals as well
Standard I/O
No loss of memory addresses to peripherals
Simpler address decoding logic in peripherals possible
When number of peripherals much smaller than address space then high-order address bits can be ignored
smaller and/or faster comparators
Standard I/O requires special instructions (e.g., IN, OUT) to move data between peripheral registers and memory

118. Timers(타이머) Timer: 시간 간격(time interval) 측정 Clock Pulse의 counting에 기반
To generate timed output events
e.g., hold traffic light green for 10 s
To measure input events
e.g., measure a car’s speed
Clock Pulse의 counting에 기반
E.g., let Clk period be 10 ns
And we count 20,000 Clk pulses
Then 200 microseconds have passed
16-bit counter would count up to 65,535*10 ns = microsec., resolution = 10 ns
Top: indicates top count reached, wrap-around
16-bit up counter
Clk
Cnt
Basic timer
Top
Reset 16

119. Counters(카운터) 카운터와 유사하나, 클럭 펄스의 수를 세는 것이 아니라 일반 입력 신호로 부터의 펄스 수를 카운트
e.g., count cars passing over a sensor
Can often configure device as either a timer or counter
16-bit up counter
Clk 16
Cnt_in
2x1 mux
Mode
Timer/counter
Top
Reset
Cnt

120. Watchdog timer
Since most industrial or mission critical embedded system cannot fail, how do we guarantee that a glitch doesn’t break the instruction flow?
Watchdog timer - 시스템의 동작을 모니터링하여, 다양한 조건 발생 시에서 RESET signal 발생
Power supply voltage goes out of range
Computer hasn’t issued a reset pulse to the timer in designated time interval
Processor
RESET IN
Output port: bit 0
Watchdog
Timer
RESET OUT
RESET INPUT

121. Interrupt interface 임베디드 시스템의 실시간성 요구에 필수적인 요소 intr request status reg
CPU
status
reg
data
mechanism PC
intr request
intr ack
data/address IR

122. Interrupts
Suppose a peripheral intermittently receives data, which must be serviced by the processor
The processor can poll the peripheral regularly to see if data has arrived – wasteful
The peripheral can interrupt the processor when it has data
Requires an extra pin or pins: Int
If Int is 1, processor suspends current program, jumps to an Interrupt Service Routine, or ISR
Known as interrupt-driven I/O
Essentially, “polling” of the interrupt pin is built-into the hardware, so no extra time!

123. Interrupts (2) ISR(interrupt service routine)의 주소? Fixed interrupt
Address built into microprocessor, cannot be changed
Either ISR stored at address or a jump to actual ISR stored if not enough bytes available
Vectored interrupt
주변장치가 주소를 제공
Common when microprocessor has multiple peripherals connected by a system bus
Compromise: interrupt address table

124. Additional interrupt issues
Maskable vs. non-maskable interrupts
Maskable: programmer can set bit that causes processor to ignore interrupt
Important when in the middle of time-critical code
Non-maskable: a separate interrupt pin that can’t be masked
Typically reserved for drastic situations, like power failure requiring immediate backup of data to non-volatile memory
Jump to ISR
Some microprocessors treat jump same as call of any subroutine
Complete state saved (PC, registers) – may take hundreds of cycles
Others only save partial state, like PC only
Thus, ISR must not modify registers, or else must save them first
Assembly-language programmer must be aware of which registers stored

125. Direct memory access (DMA)
Buffering
Temporarily storing data in memory before processing
Data accumulated in peripherals commonly buffered
Microprocessor could handle this with ISR
Storing and restoring microprocessor state inefficient
Regular program must wait
DMA controller more efficient
Separate single-purpose processor
Microprocessor relinquishes control of system bus to DMA controller
Microprocessor can meanwhile execute its regular program
No inefficient storing and restoring state due to ISR call
Regular program need not wait unless it requires the system bus

126. ARM 프로세서 (Xscale core 기반의 PXA255 중심으로)

127. References ARM Architecture reference manual
Second edition, by David Seal, Addison-wesley, 1996
ARM System Developer’s Guide Designing and Optimizing System Software
Andrew N. Sloss, Dominic Symes, and Chris Wright, Morgan 2004 KAUFMANN and Elsevier

128. PXA255 Processor Intel PXA255 Overview
High Performance 32-bit Microprocessor
Max 400MHz
Technology
0.35um, 3 layer metal CMOS, 2.6 Million transistors
256 PBGA package (17x17mm)
Xscale core 로서 ARMv5TE 기반
Modified-Harvard Architecture 가 적용된 ARM 프로세서
Separate Instruction and data cache (2 caches)

129. ARM Processor Evolution

130. Evolution of ARM Architecture
ARM Architecture Revision (Version)
특정 ISA (Instruction Set Architecture)을 가진다.

131. ARM Nomenclature

132. ARM Nomenclature (2)

133. ARM Revision History

134. CPSR and Attribute Comparison

135. ARM Processor Variants

136. ARM7 Family
ARM7core has a Von-Neumann style architecture, 3stage pipeline, ARMv4T instruction set
ARM7TDMI is the first of a new range of processors introduced in 1995 by ARM
ARM7TDMI-S : same as 7TDMI but synthesizable
ARM720T : has MMU, (capable of Linux and WinCE), unified 8Kcache (Data + Instruction)
A variation of ARM7 is ARM7EJ-S: 5-stage pipeline, executes ARMv5TEJ instructions

137. ARM9 Family ARM9 family was announced in 1997
5 stage pipeline  higher clock frequency than ARM7 family
Memory system redesign  Harvard architecture (separate D and I cache (buses)
The first processor in ARM9 family is ARM920T (Separate D + I cache, MMU  OS with virtual memory, ARMv4T instructions
ARM922T is a variation on ARM920T (half of the cache size)
ARM940T (smaller D+I cache and MPU)
The next processors in ARM9 family are based on ARM9E-S core ( synthesizable version of ARM9 core with E)
Two variations of ARM9E-S: ARM946E-S and ARM966E-S
Both execute architecture v5TE instructions
Both support optional embedded trace macrocell (ETM)
ARM946E-S includes TCM, cache, and an MPU (designed for use in embedded control applications that require deterministic real-time response)
ARM966E does not have MPU and cache extensions (but does have configurable TCMs)
The latest core in ARM9 family is ARM926EJ-S (announced in 2000)
Designed for portable Java-enabled devices such as 3G phones and PDAs)
ARM926EJ-S is the first ARM core to include Jazelle technology
Includes MMU, configurable TCMs, and D+I caches

138. ARM10 Family ARM10 was designed for performance (announced in 1999)
It extends the ARM9 pipeline to six stages
Optional vector floating-point(VFP) unit
ARM1020E is the first processor to use an ARM10E core
Separate 32K D+I caches, MMU, optional vector floating point unit, dual 64bit bus interface for increased performance
ARM1026EJ-S is very similar to ARM926EJ-S but both MPU and MMU
Has performance of ARM10 and the flexibility of an ARM926EJ-S

139. ARM11 Family
ARM1136J-S was designed for high performance and power-efficient applications (announced in 2003)
ARM1136J-S : the first processor implementation of ARMv6 architecture instructions
8stage pipeline with separate load-store and arithmetic pipelines
ARMv6 instructions include SIMD extensions for media processing
ARM1136JF-S is an ARM1136J-S with the addition of the vector floating point unit

140. Specialized Processors
StrongARM was originally co-developed by Digital Semiconductor and is now exclusively licensed by Intel
Popular for PDA (high performance and low power consumption
Harvard architecture with separate D+I caches 5 stage pipeline without Thumb instruction set
XScale is a follow-on product to the StrongARM (upto 1GHz)
Xscale executes architecture v5TE instructions
Harvard architecture and is similar to the StrongARM, Includes MMU
SC100 is designed for low-power security applications
Based on ARM7TDMI core with an MPU
Used for smart card applications

141. Memory Management of ARM
Three different types of memory management hardware of ARM
Non-protected memory
MPU: Memory Protection Unit
Simple system that uses a limited number of memory resions
MMU: Memory Management Unit
Used by Virtual memory management system of OS

142. ARM Architecture 특징 비교

143. ARM Processor Roadmap

144. ARM Roadmap

145. ARM7 과 ARM9 Core의 비교
Maximum Clock Freq. 1.8 ~ 2배 향상
Performance: 30% 향상

146. ARM Architecture 출처: ARM6 Architecture:

147. ARMv6의 성능향상기법

148. Little and Big endians Little Endian Big Endian
0x345f --- address: 0x8000: 5f x8001: 34
DNS
MSB: kr
LSB: www
Intel i386 CPUs
Big Endian
kr.ac.yu.www
0x345f  34 , 5f
IBM, Motorola
Mixed (Supports both Little and Big endians)
ARM (default: Little Endian)

149. 삼성에서 나오는 ARM 프로세서들

150. Qualcomm Processors

151. Qualcomm MSM6800

152. Qualcomm MSM3300

153. TMS320DM270

155. Intel XScale Core Architecture
Refer to Intel XScale Core Developer’s Manual
January, 2004

156. Extensions to ARM Architecture

157. Event Architecture

158. Event Priority of XScale

159. Configuration

160. MCR/MRC Format

161. LDC/STC Format when Accessing CP14

162. CP15 Registers

163. Intel PXA255 Processor Developer’s Manual January, 2004

164. System Integration Unit

165. PXA255 Pin Serial Channel 0 (USB) LCDControl Serial Channel 1
UDC-
L_DD(15:0)
Serial Channel 0 (USB)
UDC+
L_FCLK
RXD_1
L_LCLK
Serial Channel 1
LCDControl
TXD_1
L_PCLK
RXD_2
L_BIAS
Serial Channel 2 (IrDA)
TXD_2
Intelⓡ
XScale*
PXA250
[256-pins]
GP(27:0)
GPIO Ports
RXD_3
nCAS/ DQM(3:0)
Serial Channel 3 (UART)
TXD_3
nRAS/ nSDCS(3:0)
TXD_C
nOE
RXD_C
nWE
Serial Channel 4(CODEC)
SFRM_C
nCS(5:0)
Memory Control
SCLK_C
RDY
BATT_FAULT
nSDRAS
VDD_FAULT
nSDCAS
Power Management
PWR_EN
SDCKE<1:0>
SDCLK<2:0>
TCK_BYP
RD/nWR
Transceiver Control
TESTCLK
PEXTAL
nPOE
nPWE
PXTAL
nPIOR
nPIOW
TEXTAL
nPCE<2:1>
PCMCIA Bus Signals
Clocks, Reset and Test
TXTAL
PSKTSEL
nPREG
nRESET
nPWAIT
nRESET_OUT
nIOIS16
SMROM_EN
Address Bus
A<25:0>
ROM_SEL
TCK
D<31:0>
Data Bus
TDI
JTAG
TDO
VDD
TMS
VDDX
Supply
nTRST
VSS/VSSX

166. PXA255 Address Map Reserved (1280 Mbytes) SDRAM Bank 3 (64 Mbytes)
0hFFFF FFFF
Reserved (1280 Mbytes)
0hB
SDRAM Bank 3 (64 Mbytes)
0hAC
SDRAM Bank 2 (64 Mbytes)
0hA
Dynamic Memory Interface 256 Mbytes
SDRAM Bank 1 (64 Mbytes)
0hA
SDRAM Bank 0 (64 Mbytes)
0hA
Reserved (1344 Mbytes)
0h4C
Memory Mapped registers (Memory Ctl) 0h
Memory Mapped registers Interface
192 Mbytes
Memory Mapped registers (LCD) 0h
Memory Mapped registers (Peripherals) 0h
PCMCIA/CF - Slot 1
(256 Mbytes) 0h
PCMCIA Interface 512 Mbytes
PCMCIA/CF - Slot 0
(256 Mbytes) 0h
Reserved (128 Mbytes) 0h
Static Chip Select 5 (64 Mbytes) 0h
Static Chip Select 4 (64 Mbytes) 0h
Static Chip Select 3 (64 Mbytes)
Static Memory Interface (ROM, Flash, SRAM)
384 Mbytes
0h0C
Static Chip Select 2 (64 Mbytes) 0h
Static Chip Select 1 (64 Mbytes) 0h 0h
Static Chip Select 0 (64 Mbytes)

167. PXA255 기반의 Example System Intel®XScale PX255 Portable Communications
Microprocessor
UART
Tablet/ Serial
Keyboard
AC97
Infrared
USB Synchronization
Port
TFT Color
LCD
Display
SDRAM/DRAM
SMROM/ROM
Flash
Glue Logic
SRAM
Variable
Latency
I/O
PCMCIA Interface
(Flash, Modem)
Speaker
Microphone
3.686MHz
32.768KHz
손바닥 사이즈의 시스템구성

168. DMA Controller and Bridge
PXA255 Processor(1)
ASIC
Color or Grayscale
LCD Controller
RTC
OS Timer
PWM(2)
Interrupt
Controller
Clock &
Power Man.
I2S
I2C
AC97
FF_UART
BT_UART
Slow lrDA
Fast lrDA
SSP
Memory
Variable
Latency
I/O
Control
PCMCIA
& CF
Static
General Purpose I / O
Peripheral Bus
MHz
Osc
KHz
System Bus
XCVR
ROM/
Flash
SRAM
4 banks
Socket 0
Socket 1
Dynamic
SDRAM/
SMROM
DMA Controller and Bridge
CS # 0,1,2
CS # 3,4,5
0x4400_0000
XScale
Core
IMMU
DMMU
Icache
(32 Kbytes)
Dcache
Minicache
Instructions PC
Addr
Write
Buffer
Read
Load/Store Data
Megacell
NSSP
USB
Client
MMC
PXA255 Block Diargaram
DMA Controller 0x
Full Function UART 0x
Bluetooth UART 0x
I2C 0x
I2S 0x
AC x
UDC 0x
Standard UART 0x
ICP 0x
RTC 0x
OS Timer 0x40A
PWM x40B
PWM x40C
Interrupt Control 0x40D
GPIO 0x40E
Power Manager and Reset Control 0x40F
SSP 0x
MMC Controller 0x
Clocks Manager 0x
LCD Controller 0x
Memory Controller 0x
DMA Controller 0x
0x DCSR0 DMA Control / Status Register for Channel 0
0x DCSR1 DMA Control / Status Register for Channel 1
0x DCSR2 DMA Control / Status Register for Channel 2
0x C DCSR3 DMA Control / Status Register for Channel 3
0x DCSR4 DMA Control / Status Register for Channel 4
0x DCSR5 DMA Control / Status Register for Channel 5
0x DCSR6 DMA Control / Status Register for Channel 6
0x C DCSR7 DMA Control / Status Register for Channel 7
0x DCSR8 DMA Control / Status Register for Channel 8
0x DCSR9 DMA Control / Status Register for Channel 9
0x DCSR10 DMA Control / Status Register for Channel 10
0x C DCSR11 DMA Control / Status Register for Channel 11
0x DCSR12 DMA Control / Status Register for Channel 12
0x DCSR13 DMA Control / Status Register for Channel 13
0x DCSR14 DMA Control / Status Register for Channel 14
0x C DCSR15 DMA Control / Status Register for Channel 15
0x f0 DINT DMA Interrupt Register
0x DRCMR0 Request to Channel Map Register for DREQ 0
0x DRCMR1 Request to Channel Map Register for DREQ 1
0x DRCMR2 Request to Channel Map Register for I2S receive Request
0x C DRCMR3 Request to Channel Map Register for I2S transmit Request
0x DRCMR4 Request to Channel Map Register for BTUART receive Request
0x DRCMR5 Request to Channel Map Register for BTUART transmit Request.
0x DRCMR6 Request to Channel Map Register for FFUART receive Request
0x C DRCMR7 Request to Channel Map Register for FFUART transmit Request
0x DRCMR8 Request to Channel Map Register for AC97 microphone Request
0x DRCMR9 Request to Channel Map Register for AC97 modem receive Request
0x DRCMR10 Request to Channel Map Register for AC97 modem transmit Request
0x C DRCMR11 Request to Channel Map Register for AC97 audio receive Request
0x DRCMR12 Request to Channel Map Register for AC97 audio transmit Request
0x DRCMR13 Request to Channel Map Register for SSP receive Request
0x DRCMR14 Request to Channel Map Register for SSP transmit Request
0x C DRCMR15 Reserved
0x DRCMR16 Reserved
0x DRCMR17 Request to Channel Map Register for ICP receive Request
0x DRCMR18 Request to Channel Map Register for ICP transmit Request
0x C DRCMR19 Request to Channel Map Register for STUART receive Request
0x DRCMR20 Request to Channel Map Register for STUART transmit Request
0x DRCMR21 Request to Channel Map Register for MMC receive Request
0x DRCMR22 Request to Channel Map Register for MMC transmit Request
0x C DRCMR23 Reserved
0x DRCMR24 Reserved
0x DRCMR25 Request to Channel Map Register for USB endpoint 1 Request
0x DRCMR26 Request to Channel Map Register for USB endpoint 2 Request
0x C DRCMR27 Request to Channel Map Register for USB endpoint 3 Request
0x DRCMR28 Request to Channel Map Register for USB endpoint 4 Request
0x DRCMR29 Reserved
0x DRCMR30 Request to Channel Map Register for USB endpoint 6 Request
0x C DRCMR31 Request to Channel Map Register for USB endpoint 7 Request
0x DRCMR32 Request to Channel Map Register for USB endpoint 8 Request
0x DRCMR33 Request to Channel Map Register for USB endpoint 9 Request
0x DRCMR34 Reserved
0x C DRCMR35 Request to Channel Map Register for USB endpoint 11 Request
0x DRCMR36 Request to Channel Map Register for USB endpoint 12 Request
0x DRCMR37 Request to Channel Map Register for USB endpoint 13 Request
0x DRCMR38 Request to Channel Map Register for USB endpoint 14 Request
0x C DRCMR39 Reserved
0x DDADR0 DMA Descriptor Address Register Channel 0
0x DSADR0 DMA Source Address Register Channel 0
0x DTADR0 DMA Target Address Register Channel 0
0x C DCMD0 DMA Command Address Register Channel 0
0x DDADR1 DMA Descriptor Address Register Channel 1
0x DSADR1 DMA Source Address Register Channel 1
0x DTADR1 DMA Target Address Register Channel 1
0x C DCMD1 DMA Command Address Register Channel 1
0x DDADR2 DMA Descriptor Address Register Channel 2
0x DSADR2 DMA Source Address Register Channel 2
0x DTADR2 DMA Target Address Register Channel 2
0x C DCMD2 DMA Command Address Register Channel 2
0x DDADR3 DMA Descriptor Address Register Channel 3
0x DSADR3 DMA Source Address Register Channel 3
0x DTADR3 DMA Target Address Register Channel 3
0x C DCMD3 DMA Command Address Register Channel 3
0x DDADR4 DMA Descriptor Address Register Channel 4
0x DSADR4 DMA Source Address Register Channel 4
0x DTADR4 DMA Target Address Register Channel 4
0x C DCMD4 DMA Command Address Register Channel 4
0x DDADR5 DMA Descriptor Address Register Channel 5
0x DSADR5 DMA Source Address Register Channel 5
0x DTADR5 DMA Target Address Register Channel 5
0x C DCMD5 DMA Command Address Register Channel 5
0x DDADR6 DMA Descriptor Address Register Channel 6
0x DSADR6 DMA Source Address Register Channel 6
0x DTADR6 DMA Target Address Register Channel 6
0x C DCMD6 DMA Command Address Register Channel 6
0x DDADR7 DMA Descriptor Address Register Channel 7
0x DSADR7 DMA Source Address Register Channel 7
0x DTADR7 DMA Target Address Register Channel 7
0x C DCMD7 DMA Command Address Register Channel 7
0x DDADR8 DMA Descriptor Address Register Channel 8
0x DSADR8 DMA Source Address Register Channel 8
0x DTADR8 DMA Target Address Register Channel 8
0x C DCMD8 DMA Command Address Register Channel 8
0x DDADR9 DMA Descriptor Address Register Channel 9
0x DSADR9 DMA Source Address Register Channel 9
0x DTADR9 DMA Target Address Register Channel 9
0x C DCMD9 DMA Command Address Register Channel 9
0x A0 DDADR10 DMA Descriptor Address Register Channel 10
0x A4 DSADR10 DMA Source Address Register Channel 10
0x A8 DTADR10 DMA Target Address Register Channel 10
0x AC DCMD10 DMA Command Address Register Channel 10
0x B0 DDADR11 DMA Descriptor Address Register Channel 11
0x B4 DSADR11 DMA Source Address Register Channel 11
0x B8 DTADR11 DMA Target Address Register Channel 11
0x BC DCMD11 DMA Command Address Register Channel 11
0x C0 DDADR12 DMA Descriptor Address Register Channel 12
0x C4 DSADR12 DMA Source Address Register Channel 12
0x C8 DTADR12 DMA Target Address Register Channel 12
0x CC DCMD12 DMA Command Address Register Channel 12
0x D0 DDADR13 DMA Descriptor Address Register Channel 13
0x D4 DSADR13 DMA Source Address Register Channel 13
0x D8 DTADR13 DMA Target Address Register Channel 13
0x DC DCMD13 DMA Command Address Register Channel 13
0x E0 DDADR14 DMA Descriptor Address Register Channel 14
0x E4 DSADR14 DMA Source Address Register Channel 14
0x E8 DTADR14 DMA Target Address Register Channel 14
0x EC DCMD14 DMA Command Address Register Channel 14
0x F0 DDADR15 DMA Descriptor Address Register Channel 15
0x F4 DSADR15 DMA Source Address Register Channel 15
0x F8 DTADR15 DMA Target Address Register Channel 15
0x FC DCMD15 DMA Command Address Register Channel 15
Full Function UART 0x
0x FFRBR Receive Buffer Register (read only)
0x FFTHR Transmit Holding Register (write only)
0x FFIER Interrupt Enable Register (read/write)
0x FFIIR Interrupt ID Register (read only)
0x FFFCR FIFO Control Register (write only)
0x C FFLCR Line Control Register (read/write)
0x FFMCR Modem Control Register (read/write)
0x FFLSR Line Status Register (read only)
0x FFMSR Modem Status Register (read only)
0x C FFSPR Scratch Pad Register (read/write)
0x FFISR Infrared Selection Register (read/write)
0x FFDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x FFDLH Divisor Latch High Register (DLAB = 1) (read/write)
Bluetooth UART 0x
0x BTRBR Receive Buffer Register (read only)
0x BTTHR Transmit Holding Register (write only)
0x BTIER Interrupt Enable Register (read/write)
0x BTIIR Interrupt ID Register (read only)
0x BTFCR FIFO Control Register (write only)
0x C BTLCR Line Control Register (read/write)
0x BTMCR Modem Control Register (read/write)
0x BTLSR Line Status Register (read only)
0x BTMSR Modem Status Register (read only)
0x C BTSPR Scratch Pad Register (read/write)
0x BTISR Infrared Selection Register (read/write)
0x BTDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x BTDLH Divisor Latch High Register (DLAB = 1) (read/write)
I2C 0x
0x IBMR I2C Bus Monitor Register - IBMR
0x IDBR I2C Data Buffer Register - IDBR
0x ICR I2C Control Register - ICR
0x ISR I2C Status Register - ISR
0x A0 ISAR I2C Slave Address Register - ISAR
I2S 0x
0x SACR0 Global Control Register
0x SACR1 Serial Audio I2S/MSB-Justified Control Register
0x Reserved
0x C SASR0 Serial Audio I2S/MSB-Justified Interface and FIFO Status Register
0x Reserved
0x SAIMR Serial Audio Interrupt Mask Register
0x SAICR Serial Audio Interrupt Clear Register
0x C through 0x C - Reserved
0x SADIV Audio Clock Divider Register.
0x through 0x C - Reserved
0x SADR Serial Audio Data Register (TX and RX FIFO access Register).
AC97 0x
0x POCR PCM Out Control Register
0x PICR PCM In Control Register
0x MCCR Mic In Control Register
0x C GCR Global Control Register
0x POSR PCM Out Status Register
0x PISR PCM In Status Register
0x MCSR Mic In Status Register
0x C GSR Global Status Register
0x CAR CODEC Access Register
0x through 0x C - Reserved
0x PCDR PCM FIFO Data Register
0x through 0x C - Reserved
0x MCDR Mic-in FIFO Data Register
0x through 0x FC - Reserved
0x MOCR Modem Out Control Register
0x Reserved
0x MICR Modem In Control Register
0x C - Reserved
0x MOSR Modem Out Status Register
0x Reserved
0x MISR Modem In Status Register
0x C through 0x C - Reserved
0x MODR Modem FIFO Data Register
0x through 0x FC - Reserved
0x through 0x FC - Primary Audio codec Registers
0x through 0x FC - Secondary Audio codec Registers
0x through 0x FC - Primary Modem codec Registers
0x through 0x FC - Secondary Modem codec Registers
UDC 0x
0x UDCCR UDC Control Register
0x UDCCS0 UDC Endpoint 0 Control/Status Register
0x UDCCS1 UDC Endpoint 1 (IN) Control/Status Register
0x UDCCS2 UDC Endpoint 2 (OUT) Control/Status Register
0x C UDCCS3 UDC Endpoint 3 (IN) Control/Status Register
0x UDCCS4 UDC Endpoint 4 (OUT) Control/Status Register
0x UDCCS5 UDC Endpoint 5 (Interrupt) Control/Status Register
0x UDCCS6 UDC Endpoint 6 (IN) Control/Status Register
0x C UDCCS7 UDC Endpoint 7 (OUT) Control/Status Register
0x UDCCS8 UDC Endpoint 8 (IN) Control/Status Register
0x UDCCS9 UDC Endpoint 9 (OUT) Control/Status Register
0x UDCCS10 UDC Endpoint 10 (Interrupt) Control/Status Register
0x C UDCCS11 UDC Endpoint 11 (IN) Control/Status Register
0x UDCCS12 UDC Endpoint 12 (OUT) Control/Status Register
0x UDCCS13 UDC Endpoint 13 (IN) Control/Status Register
0x UDCCS14 UDC Endpoint 14 (OUT) Control/Status Register
0x C UDCCS15 UDC Endpoint 15 (Interrupt) Control/Status Register
0x UFNRH UDC Frame Number Register High
0x UFNRL UDC Frame Number Register Low
0x UBCR2 UDC Byte Count Register 2
0x C UBCR4 UDC Byte Count Register 4
0x UBCR7 UDC Byte Count Register 7
0x UBCR9 UDC Byte Count Register 9
0x UBCR12 UDC Byte Count Register 12
0x C UBCR14 UDC Byte Count Register 14
0x UDDR0 UDC Endpoint 0 Data Register
0x UDDR1 UDC Endpoint 1 Data Register
0x UDDR2 UDC Endpoint 2 Data Register
0x UDDR3 UDC Endpoint 3 Data Register
0x UDDR4 UDC Endpoint 4 Data Register
0x A0 UDDR5 UDC Endpoint 5 Data Register
0x UDDR6 UDC Endpoint 6 Data Register
0x UDDR7 UDC Endpoint 7 Data Register
0x UDDR8 UDC Endpoint 8 Data Register
0x UDDR9 UDC Endpoint 9 Data Register
0x C0 UDDR10 UDC Endpoint 10 Data Register
0x4060 0B00 UDDR11 UDC Endpoint 11 Data Register
0x4060 0B80 UDDR12 UDC Endpoint 12 Data Register
0x4060 0C00 UDDR13 UDC Endpoint 13 Data Register
0x4060 0E00 UDDR14 UDC Endpoint 14 Data Register
0x E0 UDDR15 UDC Endpoint 15 Data Register
0x UICR0 UDC Interrupt Control Register 0
0x UICR1 UDC Interrupt Control Register 1
0x USIR0 UDC Status Interrupt Register 0
0x C USIR1 UDC Status Interrupt Register 1
Standard UART 0x
0x STRBR Receive Buffer Register (read only)
0x STTHR Transmit Holding Register (write only)
0x STIER Interrupt Enable Register (read/write)
0x STIIR Interrupt ID Register (read only)
0x STFCR FIFO Control Register (write only)
0x C STLCR Line Control Register (read/write)
0x STMCR Modem Control Register (read/write)
0x STLSR Line Status Register (read only)
0x STMSR Reserved
0x C STSPR Scratch Pad Register (read/write)
0x STISR Infrared Selection Register (read/write)
0x STDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x STDLH Divisor Latch High Register (DLAB = 1) (read/write)
ICP 0x
0x ICCR0 ICP Control Register 0
0x ICCR1 ICP Control Register 1
0x ICCR2 ICP Control Register 2
0x C ICDR ICP Data Register
0x Reserved
0x ICSR0 ICP Status Register 0
0x ICSR1 ICP Status Register 1
RTC 0x
0x RCNR RTC Count Register
0x RTAR RTC Alarm Register
0x RTSR RTC Status Register
0x C RTTR RTC Timer Trim Register
OS Timer 0x40A0 0000
0x40A OSMR<0> OS Timer Match Registers<0>
0x40A OSMR<1> OS Timer Match Registers<1>
0x40A OSMR<2> OS Timer Match Registers<2>
0x40A0 000C OSMR<3> OS Timer Match Registers<3>
0x40A OSCR OS Timer Counter Register
0x40A OSSR OS Timer Status Register
0x40A OWER OS Timer Watchdog Enable Register
0x40A0 001C OIER OS Timer Interrupt Enable Register
PWM 0 0x40B0 0000
0x40B PWM_CTRL0 PWM 0 Control Register
0x40B PWM_PWDUTY0 PWM 0 Duty Cycle Register
0x40B PWM_PERVAL0 PWM 0 Period Control Register
PWM 1 0x40C0 0000
0x40C PWM_CTRL1 PWM 1Control Register
0x40C PWM_PWDUTY1 PWM 1 Duty Cycle Register
0x40C PWM_PERVAL1 PWM 1 Period Control Register
Interrupt Control 0x40D0 0000
0x40D ICIP Interrupt Controller IRQ Pending Register
0x40D ICMR Interrupt Controller Mask Register
0x40D ICLR Interrupt Controller Level Register
0x40D0 000C ICFP Interrupt Controller FIQ Pending Register
0x40D ICPR Interrupt Controller Pending Register
0x40D ICCR Interrupt Controller Control Register
GPIO 0x40E0 0000
0x40E GPLR0 GPIO Pin-Level Register GPIO<31:0>
0x40E GPLR1 GPIO Pin-Level Register GPIO<63:32>
0x40E GPLR2 GPIO Pin-Level Register GPIO<80:64>
0x40E0 000C GPDR0 GPIO Pin Direction Register GPIO<31:0>
0x40E GPDR1 GPIO Pin Direction Register GPIO<63:32>
0x40E GPDR2 GPIO Pin Direction Register GPIO<80:64>
0x40E GPSR0 GPIO Pin Direction Register GPIO<31:0>
0x40E0 001C GPSR1 GPIO Pin Output Set Register GPIO<63:32>
0x40E GPSR2 GPIO Pin Output Set Register GPIO<80:64>
0x40E GPCR0 GPIO Pin Output Clear Register GPIO<31:0>
0x40E GPCR1 GPIO Pin Output Clear Register GPIO <63:32>
0x40E0 002C GPCR2 GPIO Pin Output Clear Register GPIO <80:64>
0x40E GRER0 GPIO Rising-Edge Detect Register GPIO<31:0>
0x40E GRER1 GPIO Rising-Edge Detect Register GPIO<63:32>
0x40E GRER2 GPIO Rising-Edge Detect Register GPIO<80:64>
0x40E0 003C GFER0 GPIO Falling-Edge Detect Register GPIO<31:0>
0x40E GFER1 GPIO Falling-Edge Detect Register GPIO<63:32>
0x40E GFER2 GPIO Falling-Edge Detect Register GPIO<80:64>
0x40E GEDR0 GPIO Edge Detect Status Register GPIO<31:0>
0x40E0 004C GEDR1 GPIO Edge Detect Status Register GPIO<63:32>
0x40E GEDR2 GPIO Edge Detect Status Register GPIO<80:64>
0x40E GAFR0_L GPIO Alternate Function Select Register GPIO<15:0>
0x40E GAFR0_U GPIO Alternate Function Select Register GPIO<31:16>
0x40E0 005C GAFR1_L GPIO Alternate Function Select Register GPIO<47:32>
0x40E GAFR1_U GPIO Alternate Function Select Register GPIO<63:48>
0x40E GAFR2_L GPIO Alternate Function Select Register GPIO<79:64>
0x40E GAFR2_U GPIO Alternate Function Select Register GPIO 80
Power Manager and Reset Control 0x40F0 0000
0x40F PMCR Power Manager Control Register
0x40F PSSR Power Manager Sleep Status Register
0x40F PSPR Power Manager Scratch Pad Register
0x40F0 000C PWER Power Manager Wake-up Enable Register
0x40F PRER Power Manager GPIO Rising-Edge Detect Enable Register
0x40F PFER Power Manager GPIO Falling-Edge Detect Enable Register
0x40F PEDR Power Manager GPIO Edge Detect Status Register
0x40F0 001C PCFR Power Manager General Configuration Register
0x40F PGSR0 Power Manager GPIO Sleep State Register for GP[31-0]
0x40F PGSR1 Power Manager GPIO Sleep State Register for GP[63-32]
0x40F PGSR2 Power Manager GPIO Sleep State Register for GP[84-64]
0x40F0 002C - Reserved
0x40F RCSR Reset Controller Status Register
SSP 0x
0x SSCR0 SSP Control Register 0
0x SSCR1 SSP Control Register 1
0x SSSR SSP Status Register
0x C SSITR SSP Interrupt Test Register
0x SSDR (Write / Read) SSP Data Write Register/SSP Data Read Register
MMC Controller 0x
0x MMC_STRPCL Control to start and stop MMC clock
0x MMC_STAT MMC Status Register (read only)
0x MMC_CLKRT MMC clock rate
0x C MMC_SPI SPI mode control bits
0x MMC_CMDAT Command/response/data sequence control
0x MMC_RESTO Expected response time out
0x MMC_RDTO Expected data read time out
0x C MMC_BLKLEN Block length of data transaction
0x MMC_NOB Number of blocks, for block mode
0x MMC_PRTBUF Partial MMC_TXFIFO FIFO written
0x MMC_I_MASK Interrupt Mask
0x C MMC_I_REG Interrupt Register (read only)
0x MMC_CMD Index of current command
0x MMC_ARGH MSW part of the current command argument
0x MMC_ARGL LSW part of the current command argument
0x C MMC_RES Response FIFO (read only)
0x MMC_RXFIFO Receive FIFO (read only)
0x MMC_TXFIFO Transmit FIFO (write only)
Clocks Manager 0x
0x CCCR Core Clock Configuration Register
0x CKEN Clock Enable Register
0x OSCC Oscillator Configuration Register
LCD Controller 0x
0x LCCR0 LCD Controller Control Register 0
0x LCCR1 LCD Controller Control Register 1
0x LCCR2 LCD Controller Control Register 2
0x C LCCR3 LCD Controller Control Register 3
0x FDADR0 DMA Channel 0 Frame Descriptor Address Register
0x FSADR0 DMA Channel 0 Frame Source Address Register
0x FIDR0 DMA Channel 0 Frame ID Register
0x C LDCMD0 DMA Channel 0 Command Register
0x FDADR1 DMA Channel 1 Frame Descriptor Address Register
0x FSADR1 DMA Channel 1 Frame Source Address Register
0x FIDR1 DMA Channel 1 Frame ID Register
0x C LDCMD1 DMA Channel 1 Command Register
0x FBR0 DMA Channel 0 Frame Branch Register
0x FBR1 DMA Channel 1 Frame Branch Register
0x LCSR LCD Controller Status Register
0x C LIIDR LCD Controller Interrupt ID Register
0x TRGBR TMED RGB Seed Register
0x TCR TMED Control Register
Memory Controller 0x
0x MDCNFG SDRAM Configuration Register 0
0x MDREFR SDRAM Refresh Control Register
0x MSC0 Static Memory Control Register 0
0x C MSC1 Static Memory Control Register 1
0x MSC2 Static Memory Control Register 2
0x MECR Expansion Memory (PCMCIA/Compact Flash) Bus Configuration Register
0x C SXCNFG Synchronous Static Memory Control Register
0x SXMRS MRS value to be written to SMROM
0x MCMEM0 Card interface Common Memory Space Socket 0 Timing Configuration
0x C MCMEM1 Card interface Common Memory Space Socket 1 Timing Configuration
0x MCATT0 Card interface Attribute Space Socket 0 Timing Configuration
0x MCATT1 Card interface Attribute Space Socket 1 Timing Configuration
0x MCIO0 Card interface I/O Space Socket 0 Timing Configuration
0x C MCIO1 Card interface I/O Space Socket 1 Timing Configuration
0x MDMRS MRS value to be written to SDRAM
0x BOOT_DEF Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL values.

169. PXA255 Processor(2) Micro-architecture Execution Core IRQ FIQ BTB
Branch Target Buffer
Trace Buffer
Instruction Cache 32KBytes
Data Cache 32 KBytes
Mini D-Cache 2 KBytes
MMU
Write Buffer
System Management
Debug
JTAG
CP0 Multiplier / Accumulator
CP 15 Config Registers
CP 14 Performance Monitoring
IRQ
FIQ
Interrupt
Request
Coprocessor
Interface
Instruction
Execution
Core
Data
Address
Core Memory Bus
Mini I-Cache 2 KBytes
BTB
128 entry, direct mapped cache
brnach명령의 주소
brnach명령과 관계된 Target주소
a previous history of the branch being taken or not taken
history의 내용은 4개 중에 하나로 구성되어 있다.
strongly taken/weakly taken/weakly not-taken/strongly not-taken
사용여부는 CP15 C1에 의해서 결정된다.
성공적으로 예측된 branch는 superpipeline에서의 branch-latency penalty를 회피한다.
실패한 예측 branch의 결과는 4-5 branch-latency penalty를 초래한다.
현재의 instruction address를 갖져온다. 그리고 tag를 취하기 위해서 현재의 어드레스에서 [8:2]를 취한다.
그리고 instruction address와 tag값을 비교한다. 비교하는 비트는 [31:9,1]이다.
주소가 일치하고 history bit가 이전에 자주 사용되어졌던 분기 주소이면, BTB는 다음의 instruction address로 간주하고 data(target address)를 전송한다.
Update policy
- branch instruction이 실행된 경우
- the branch was taken
- 현재 branch가 BTB에 없는 경우
BTB Control
Disabling/Enabling
Reset시 : disable
Enable : CP15 C1.11(Z) = 1
Invalidation
- reset
- CP15 C7에서 BTB를 invalidate한 경우(7-11)
- Processo ID register에 값이 쓰여진 경우
- CP15 C7을 통해서 instruction cache가 invalidate한 경우

170. PXA255 Processor(3) XScale Core Architecture Features
Instruction Cache Kbytes 32 Ways
Lockable by line
Micro- Processor 7 Stage pipeline
Data Cache Max 32 Kbytes 32 ways WR-Back or
WR-Through Hit under miss
Debug Hardware Breakpoints Branch History Table
MAC Single cycle Throughput (16*32) 16-bit SIMD 40-bit accumulator
Power Mgnt Ctrl
Write Buffer 8 entries Full coalescing
JTAG
Data Ram Max 28 Kbytes Re-map of data cache
Branch Target Buffer 128 entries
IMMU 32 entry TLB Fully associative Lockable by entry
DMMU 32 entry TLB Fully associative Lockable by entry
Fill Buffer 4~8 entries
Performance Monitoring
Mini-Data Cache 2 Kbytes 2 ways
MAC - Memory Access Controller
The Intel® XScale™ microarchitecture provides these features:
• ARM* Architecture Version 5TE ISA compliant.
— ARM* Thumb Instruction Support
— ARM* DSP Enhanced Instructions
• Low power consumption and high performance
• Intel® Media Processing Technology
— Enhanced 16-bit Multiply
— 40-bit Accumulator
• 32-KByte Instruction Cache
• 32-KByte Data Cache
• 2-KByte Mini Data Cache
• 2-KByte Mini Instruction Cache
• Instruction and Data Memory Management Units
• Branch Target Buffer
• Debug Capability via JTAG Port
ASSP Application Specific Standard Product.
API Application Programming Interface.
BTB Branch Target Buffer
TLB Translation Look-aside Buffer.
Coalescing 기존 저장 오퍼레이션과 함께 새로운 저장 오퍼레이션을 같이 가지고 오는것을 의미한다.

171. Register File Operand Shifter
PXA255 Processor(4)
XScale Core
32Bit RISC
32Bit registers
32Bit instructions
Longword aligned
32Bit datapaths
7~8 stage pipeline
ALU Execute
Register File Operand Shifter
Instruction Fetch1
Write Back
State Execute PC
PC - 12
PC - 16
Instruction Fetch2
PC - 4
Instruction Decode
PC - 8
Data Cache Access
Data Cache Writeback
Multiplier Stage1
Multiplier Stage X
Multiplier Stage2 F1 RF X1 F2 ID M1 M2 Mx X2
XWB
DWB D2 D1
MAC pipeline
Main execution
pipeline
Memory pipeline

172. ARM HOST BUS, ARM SYSTEM BUS
PXA255 Processor(5)
Advanced Microcontroller Bus Architecture
CPU버스 : A, B, ALU BUS로 구성
Arbiter
TIC
EBI
ARM
Bus I/F
Bridge
On-chip
RAM
Decoder
Timer
Remap /
Pause
Interrupt
Controller
Reset
External
ROM
AHB or ASB
APB
Slow
Peripherals
ARM HOST BUS, ARM SYSTEM BUS
프로세서 내부에 내장된 고속 장치 연결
ARM PERIPHERAL BUS
저속으로 동작하는 장치 연결

173. PXA255 Processor(6) Memory Model MMU On-chip Caches Core Memory
Virtual Addresses
Physical Addresses
Buffers
Controller
PX255 Processor

174. PXA255 Processor(7) PXA255 BUS Reads PXA255
Cache line fills read 8 words
Read Allocate
Round robin replacement
Half Core Clock
Core Clock
System Memory
PXA255
D[0:31]
Instruction
hit
32KB
I- Cache PC
Instructions
&
Data
miss
A[0:25]
Memory
Controller
A[0:31]
Read
Buffer
A[0:31]
I-MMU
VA[0:31]
XScale
Core
D[0:31]
D[0:31]
A[0:31]
D-MMU
VA[0:31]
External Bus
System Bus
miss
32 bytes
32KB
D-Cache
Addr
hit
D[0:31]
Data

175. PXA255 Processor(8) PXA255 PXA255 BUS Writes No wirte to I-Cache
Write Back D-Cache
Software coherency needed between caches
Not write allocate
System Memory
Half Core Clock
Core Clock
PXA255
A[0:31]
D-MMU
VA[0:31]
Data
Dirty Bits
XScale
Core
A[0:25]
A[0:31]
Write
Buffer
(8entries)
Memory
Controller
32 bytes
D[0:31]
D[0:31]
32KB
D-Cache
External Bus
System Bus
Addr
Data
D[0:31]

176. What happens on a write?
Write through—The information is written to both the block in the cache and to the block in the lower-level memory.
Write back—The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced.
is block clean or dirty?
Pros and Cons of each?
WT: read misses cannot result in writes
WB: no writes of repeated writes
WT always combined with write buffers so that don’t wait for lower level memory

177. Write Buffer for Write Through
Processor
Cache
Write Buffer
DRAM
A Write Buffer is needed between the Cache and Memory
Processor: writes data into the cache and the write buffer
Memory controller: write contents of the buffer to memory
Write buffer is just a FIFO:
Write Buffer는 쓰는 경우의 성능 향상을 위해 존재
캐시 메모리는 명령어, 데이터를 읽을 경우의 성능 향상
CPU가 쓰기 동작을 하는 동안에도 다른 처리를 계속할 수 있도록, 주소와 데이터가 write buffer에 저장
버스의 사용권한이 write buffer에 주어지면 외부장치에 write
You are right, memory is too slow. We really didn't writ e to the memory directly. We are writing to a write buffer.
Once the data is written into the write buffer and assuming a cache hit, the CPU is done with the write. The memory controller will then move the write buffer’s contents to the real memory behind the scene.
The write buffer works as long as the frequency of store is not too high. Notice here, I am referring to the frequency with respect to time, not with respect to number of instructions.
Remember the DRAM cycle time we talked about last time. It sets the upper limit on how frequent you can write to the main memory.
If the store are too close together or the CPU time is so much faster than the DRAM cycle time, you can end up overflowing the write buffer and the CPU must stop and wait.
+2 = 60 min. (Y:40)

178. Cache organization DATA RAM 32set 8word 4byte 1 2 3 4 5 6 7 Tag CAM31 12 11 10 9 8 7 6 5 4 3 2 1
Line
offset
Virtual address
Tag
Index
32set
8word
4byte
DATA
RAM 1 2 3 4 5 6 7 31 30 29 28 32
lines
Fully Associativety 가 16개 중복됨
1line : 8word : 32byte
1set : 32line : 256 word : 1024 byte
동일한 하위번지 가지고 있는 address의 집합 – 512배수로 됨
I or D cache : 16set : 512line : 4096 word : 16Kbyte
데이터가 연속인 주소 공간에 있는 경우 각각 set의 동일한 line이 연속적인 주소 공간임
Index를 통해 16개의 set중에 해당하는 set을 선택한다.
해당하는 set에 선택한 TAG의 값과 일치하는 값이 있으면 hit 이므로 해당하는 값을 데이터 라인에 쓰거나 읽는다.
Miss인 경우는 메모리로부터 데이터를 가지고 온다.
Index가 많을 수록 연속된 데이터를 가질 확률이 높다.
Tag
CAM
To From
CPU 3 2 1

179. PXA255 - 명령어 캐시 명령어 캐시(Instruction Cache) 32KB Instruction Cache
1024 lines of 32bytes(8words)
Uses the virtual address
32-way 32-set associative
Round-Robin replacement
Mapped via MMU page C bits
MMU가 enable 되었을 경우에는 memory management table에 있는 C비트에 의해서 제어된다.
MMU가 disable 되었을 경우에는 모든 어드레스에 대하여 C=1인 된다.
C=1 또는 MMU가 disable 상태인 경우 miss인 경우
8word의 line fetch가 수행이 되어 Round-robin replacement에 의해서 Cache bank가 대치된다.
MMU가 enable되고 C=0인 경우에는 virtual address에 해당하는 외부 메모리로부터 single word를 읽어오고, cache에 쓰여지지 않는다.
Instructions
IMMU
32 Kbytes
I-cache
XScale
Core PC
Main D-cache
&
Mini-D-cache
DMMU
Address
Data

180. PXA255 - 데이터 캐시 데이터 캐시(Data Caches)
Two Data Caches(Main Data Cache, Mini Data Cache)
Both: writeback, read allocate, virtual
Mapped via MMU page B, C bits
Main Data Cache, 32KB
32-way 32-set associative
Round-Robin replacement
B=1 & C=1
Mini Data Cache, 2KB
2-way set associative
Least Recently Used(LRU) replacement
B=0 & C=1
Instructions
IMMU
16 Kbyte
I-cache
XScale
Core PC
Main D-cache
&
Mini-D-cache
DMMU
Address
Data

181. PXA255 - Read Buffer PXA255 Read Buffer Data prefetcher
saves processor waiting
load & calculate in parallel
for Read-Only data
supplements the data cache
Under software control
Coprocessor 15, register #9
4 entries, 32 bytes each
Loads of 1, 4, 8 words
Replace or invalidate data
Instructions
I-cache
XScale
Core PC
D-cache
&
mini-D-cache
Address
Data
Write
Buffer
128 Byte
Read
Buffer
System Bus

182. Physical Addresses Space Virtual Addresses Space
PXA255 Memory Management
Physical Addresses Space
Virtual Addresses Space
MMU
System Memory
PXA255
ITLB
I-CACHE 32 C A PA VA
XScale
Core
Instructions
DTLB
D-CACHE B C A PA VA
Data
TLB Miss
Translation Table
Base Register
Descriptors
Coprocessor에 의한 MMU 지원

183. PXA255 Processor - CP15 CP15 Register structure Register Purpose
ID Register 1
Control 2
Translation Table Base 3
Domain Access Control 5
Fault Staus 6
Fault Address 7
Cache Operations 8
TLB Operations 9
Read Buffer Operations 10
TLB lockdown 13
Process ID Mapping 14
Debug Support 15
Test & Clock Control
4,11~12
UNUSED

184. PXA255 CoProcessor CP15 register C0 C1 C2 C3 C5 C6 C13
C0 >> : Intel Manufacturer
4..15 : Part Number
C1 >> M bit0 MMU
0 – On-chip memory-management unit disabled
1 – On-chip memory-management unit enabled
A bit1 Address fault
0 – Alignment fault disabled
1 – Alignment fault enable
C bit2 D-Cache
0 – Data cache disabled
1 – Data cache enabled
W bit3 Write Buffer
0 – Write buffer disabled
1 – Write buffer enabled
P bit4 32-bit/26-bit exception handlers. should always be 1.
D bit5 32-bit/26-bit Data address range. should always be 1.
L bit6 Inplementation defined. should always be 1.
B bit7 Little – Bigendian
0 – Little endian operation
1 – Big endian operation
S bit8 System
R bit9 ROM
F bit10 ;
Z bit11 ;
I bit12 I-Cache
0 – Instruction cache disabled
1 – Instruction cache enabled
V bit13 Virtual interrupt vector adjust
0 – Base address of interrupt vectors is 0x0000_0000
1 – Base address of interrupt vectors is 0xFFFF_0000
RR bit14 ;
C2 >> ; MMU 가 사용하는 Page table 의 Base 번지
C3 >> Domain Register - 메모리접근권한 Manager or Client
C5 >> Fault Status
C6 >> Fault address / Page Fault 상태와 주소 C6
C13

185. PXA255 Processor - SCM System Control Module
Power management controller
Supporting normal, idle and sleep modes
81 general purpose I/O ports
Generate FIQ, IRQ, “wakeup” interrupts
Interrupt controller
Routes all system (GPIOs, LCD, Serial Channel) interrupts to either IRQ or FIQ
Multi-channel DMA controller
Software programmable to any serial port and LCD
Supporting External DMA
Real time clock and timer
32 bit counter/comparator
32.7 kHz crystal - accuracy +/- 5 sec/month
OS timer with alarm register
3.68 MHz crystal - fine grain timing interrupts

186. PXA255 - running mode Summary of running mode of PXA255
Power on, nRESET asserted
HARDWARE RESET
nRESET
negated
nRESET
asserted
nRESET asserted
nRESET asserted
RUN
Wait for interrupt
instruction
Force sleep bit set, or VDD
or battery fault pins asserted
System or
peripheral unit
interrupt
GPIO or RTC
alarm interrupt
IDLE
SLEEP
VDD or battery fault pins asserted
CPU clock held low, all other
resources active, wait for interrupt
Wait for wake-up event

187. PXA255 Processor - GPIO General Purpose I/O
GPIO[58:73] = dual panel color or 16 bit parallel input on LCD
GPIO[23:27] = SPI if both synchronous serial protocols are required in a single system
Modem control signals for UART (CTS, RTS, CD, etc) implemented via GPIO signals
4-5 GPIOs required for full PCMCIA support
3 GPIOs required for Intel® SA-1111 Interface

188. PXA255 General Purose I/O Block Diagram
Pin Direction Register(GPDR)
Alternate Function
Register(GAFR)
Pin Set
Registers(GPSR)
Edge Detect Status Register(GEDR)
Rising Edge Detect Enable Register(GRER)
Falling Edge Detect Enable Register(GFER)
Edge Detect
Pin-Level Register(GPLR) 1
Alternate Function (Output)
Alternate Function (Input)
Pin Clear
Registers(GPCR) 2 3
Power Manager
Sleep Wake-up logic
0x40E0_000C/10/14
GPDR
1 : 출력
0 : 입력
0x40E0_0054/58/5C
0x40E0_0060/64/68
Base Address 0x40E0_0000
0x40E0_0048/4C/50
0x40E0_0030/34/38
0x40E0_003C/40/44
0x40E0_0000/04/08
GPIO 는 총 84개가 존재한다.
Intel PXA255 Developer’s Manual Page 4-1. 참조
GPDR - GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
GAFR - GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L,GAFR1_U,GAFR2_L,GAFR2_U)
GPSR - GPIO Pin Output Set Register
GPCR - GPIO Pin Output Clear Register
GEDR - GPIO Edge Detect Status Register
GRER - GPIO Rising Edge Detect Enable Register
GFER - GPIO Falling Edge Detect Enable Register
GPLR - GPIO Pin Level Register

189. PXA255 Interrupt controller
Level Register(ICLR)
All Other Qualified interrupt Bits
0 : IRQ
1 : FIQ
40D0 0008
XScale CORE 23 23
CCR[DIM]=0 & IDLE mode=‘1’
Interrupt Controller
Mask Register (ICMR)
40D0 0004
FIQ
Interrupt Source Bit
CPSR.6(F)
Interrupt Controller
Pending Register (ICPR)
40D0 0010
IRQ
Interrupt Controller
IRQ Pending Register (ICIP)
CPSR.7(I)
40D0 0000
Intel PXA255 Developer’s Manual Page 참조
ICIP - Interrupt Controller IRQ Pending register
ICFP - Interrupt Controller FIQ Pending register
ICPR - Interrupt Controller Pending register
ICMR - Interrupt Controller Mask register
ICLR - Interrupt Controller Level register
ICCR - Interrupt Controller Control register
Interrupt Controller
FIQ Pending Register (ICFP)
40D0 000C
40D : Interrupt controller control register (ICCR)
ICCR.0 : disable idle mask(DIM)

190. Universal Serial Bus
USB: Standard used for device/peripheral interconnect in PC market.
Intel® PXA250 is Client not Hub
Differential signaling
Half-duplex
Individual bits encoded with NRZI
Bit stuffing keeps receiver synchronized
Hand-held use USB to synchronize to a desktop PC
USB
UDC+ UDC-
리눅스에서는 이 모드를 통해 인터럽트 핸들러 구현 fiq안씀 => 수퍼바이저모드로 바꿈..

191. DMAC Block Diagram Memory Controller DMA Controller DSCR 0 DDADR 0
System Bus(internal)
Control Register
DMA Controller
16 DMA Channels
Channel 15
DSCR 0
DREQ[1:0]
(external)
Channel 0
DDADR 0
DMA_IRQ
(internal)
DSADR 0
DRCMR 0
DTADR 0
디바이스가 CPU를 거치지 않고 직접 메모리를 읽고 쓸 수 있는 방법
리눅스에서는 이 모드를 통해 인터럽트 핸들러 구현 fiq안씀 => 수퍼바이저모드로 바꿈..
DCMD 0
PREQ[37:0]
(internal)
DINT
Peripheral Bus
(internal)

192. Serial Infrared Datalink
IrDA: Infrared Data Association Standard v1.1
150 members including Digital
HP-SIR at 115kbps and 4PPM at 4Mbps
UART datastream divided by 16
Pulse then fed to IR transceiver
4PPM encodes 2 data bits at a time
Each period divided into 4-125ns time periods
125ns pulse, period 1 represents 00; period 2 represents 01, etc
Loopback for diagnostics
HandHelds talk IrDA with Laptops, PDAs & Printers
IrDA
or UART
RXD 2 TXD 2
리눅스에서는 이 모드를 통해 인터럽트 핸들러 구현 fiq안씀 => 수퍼바이저모드로 바꿈..

193. UART Universal Asynchronous Receiver/Transmitter
UART: RS-232, Infamous PC ‘Com’ ports
Operates to 230 Kbits/s
Level shifters needed for 5V logic (TTL)
Loopback for diagnostics
Data is byte wide if DMA used
HandHelds talk RS232 for synchronization, communication, keyboard I/O, software loading, etc
Primary debug connection for ARM Software Development Toolset
UART
RXD 3 TXD 3
리눅스에서는 이 모드를 통해 인터럽트 핸들러 구현 fiq안씀 => 수퍼바이저모드로 바꿈..

194. PXA255 - H/W Interface(1) RESET(EMPOS II 예) uP Reset Circuit MAX811T
Voltage Monitor ( 3V~3.15 )
Manual Reset Input ( Push button – “Low” )
Multi-ICE Reset
Reset Output to Flash
PXA255
RESET_IN
RESET_OUT MR
RESET
MAX811T 3 1 5 7
JTAG_RST
JTAG PORT
J20

195. PXA255 - H/W Interface(2) Flash memory
3Volt Intel Strata Flash - 28F128
32Bit Data Bus
Size : 32MByte -128Mbit (16Mbyte) * 2 EA
MSC0 - Static Chip Select 0 (Bank 0)
Base Address = 0x0000_0000
PXA255
Memory
Controller
Interface
ADDR [10..23]
DATA [0..32]
Flash
16Bit Low
16Bit High
D[0..15]
D[16..31]
CS0
RESET OE
MSC0 Register => 0x4800_0008

196. PXA255 - H/W Interface(3) Static RAM (SRAM) Samsung K6R4016V1C
3Volt High-Speed CMOS Static RAM
32Bit Data Bus / 1Mbyte
MSC1 - Static Chip Select 3 (Bank 3)
Base Address = 0x0C00_0000
PXA255
Memory
Controller
Interface
ADDR [10..23]
DATA [0..32]
SRAM
16Bit Low
16Bit High
D[0..15]
D[16..31]
DQM[0..1]
DQM[2..3]
CS3 WE OE
MSC1 Register => 0x4800_000C

197. PXA255 - H/W Interface(4) SDRAM (SDRAM) PXA255
Samsung Synchronous DRAM - K4S561632
32Bit Data Bus
256Mbit - 4M x 16Bit x 4 Bank
Size : 64MByte -256Mbit (32Mbyte) * 2 EA
SDRAM Bank 0 - Dynamic Memory
Base Address = 0xA000_0000
PXA255
Memory
Controller
Interface
ADDR [10..24]
DATA [0..32]
SDRAM
16Bit Low
SRAM
16Bit High
D[0..15]
D[16..31]
DQM[0..1]
DQM[2..3]
nSDCS0 WE
RAS/CAS
SDCLK1/SDCKE1
MDCNFG -> 0x4800_0000
MDREFR -> 0x4800_0004
MDMRS -> 0x4800_0040

198. PXA255 - H/W Interface(5) PCMCIA / CF PXA255 SOCKET 0 D[15:0] D[15:0]
DIR OE#
nPIOR
nPOE
A(25:0)
OE#
WE#
IOR#
IOW#
REG#
MA(25:0)
nPWE
nPIOW
nPREG
nPCE(1:2)
CE(1:2)#
nPWAIT
nPIOS16
WAIT#
IOIS16#
SOCKET 1
D[15:0]
DIR OE#
GPIO(7)
CD1#
CD2#
GPIO(12)
CD1#
CD2#
GPIO(11)
RDY/BSY#
GPIO(10)
RDY/BSY#
PSKTSEL

199. PXA255 - H/W Interface(6) PS2 Keyboard / Mouse Holtek HT6542B
8Bit Data Bus
8MHz Operating
Support PS/2 compatible mouse
PXA255
HT6542B
MD(31:0)
D(7:0)
DIR OE#
DIR OE#
KBCO
KBCI
RD_nWR
KBDO
HT6542_CS
KBDI
KEYBOARD
Address
nCS1
Decoder
nCS2
CS#
MSCO
nCS3
nCS4
MSCI DQ
RESET#
MSDO
MSDI
MOUSE
MA(25:0) A0
nOE
RD#
nPWE
WR#
GPIO(19)
KB_INT
GPIO(9)
MS_INT

200. PXA255 - H/W Interface(7) PXA255 Audio Codec Cirrus Logic CS4202
AC’ Compliant
20-bit Stero D/A Converters
18-bit Stero A/D Converters
MIC Input / Headphone Output
PXA255
AC’97
Controller
Unit
(ACUNIT)
nACRESET
CS4202
AC’97 Primary CODEC
SDATA_OUT
SYNC(48 kHz)
SDATA_IN_0
BITCLK(12.288MHz
Intel PXA255 Developer’s Manual Page Chapter 13 참조
AC97 0x
0x POCR PCM Out Control Register
0x PICR PCM In Control Register
0x MCCR MIC In Control Register
0x C GCR Global Control Register
0x POSR PCM Out Status Register
0x PISR PCM In Status Register
0x MCSR MIC In Status Register
0x C GSR Global Status Register
0x CAR CODEC Access Register
0x through 0x C - Reserved
0x PCDR PCM FIFO Data Register
0x through 0x C - Reserved
0x MCDR MIC-in FIFO Data Register
0x through 0x FC - Reserved
0x MOCR Modem Out Control Register
0x Reserved
0x MICR Modem In Control Register
0x C - Reserved
0x MOSR Modem Out Status Register
0x Reserved
0x MISR Modem In Status Register
0x C through 0x C - Reserved
0x MODR Modem FIFO Data Register
0x through 0x FC - Reserved
0x through 0x FC - Primary Audio codec Registers
0x through 0x FC - Secondary Audio codec Registers
0x through 0x FC - Primary Modem codec Registers
0x through 0x FC - Secondary Modem codec Registers

201. PXA255 - H/W Interface(8) Ethernet Controller PXA255
SMSC 10/100 Ethernet Single Chip LAN91C111
Internal 32Bit Wide Data Path
8Kbytes Internal Memory (Receive and Transmit FIFO Buffers)
External 25MHz-output pin for an external PHY and MAC
MSC0,1 - Static Chip Select 1,2 (Bank 1,2)
Base Address = 0x04000_0000 (Pri) 0x0800_0000(sec)
PXA255
MD(31:0)
T/F
Primary Ethernet
Secondary Ethernet
ADDR (15:2)
D(31:0)
DIR OE#
Logic
nCS1
nCS2
nCS3
nCS4
RD_nWR
nPWE
nOE
MA(25:0)
nDQM(3:0)
WE#
OE#
A(15:2)
DQM(3:0)#
GPIO(0)
GPIO(1)
INTR0

202. PXA255 - H/W Interface(9) Push Switches 8Bit Read [ D0~D7 ]
Base Address = 0x1050_0000

203. PXA255 - H/W Interface(10) Discrete LED’s 8Bit Write [ D0~D7 ]
Base Address = 0x1060_0000

204. PXA255 - H/W Interface(11) 7 Segment LED’s 16Bit Write [ D0~D7 ]
Base Address = 0x1030_0000 [ Low 2 Segment ]
0x1040_0000 [ High 2 Segment ]

205. PXA255 - H/W Interface(12) Character LCD 8Bit Data Write [ D0~D7 ]
3Bit Control Write [ D8~D10]
Base Address = 0x1060_0000
20 Characters x 2 Lines / Backlight Type