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Built-In Self-Test for Radio Frequency System-On-Chip Bruce Kim The University of Alabama
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2 Outline Proposed BIST Architecture Developed Equations Measurement Results Conclusions
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3 Motivation Today System-On-Board (SOB) Future System-On-Chip (SOC)
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4 RF Testing Expensive Labor intensive
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5 What is BIST (Built-In Self-Test)? A test technique which allows the SOC to evaluate its own quality without expensive external equipment.
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6 Test Flow Functional Test Proposed BIST (Go-No Go) Singulated Wafer Level Testing Package Proposed BIST Functional Testing
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7 Wireless Radio Duplexer VGA LO VGA ADC DSP DAC LO Phase Shifter LO Phase Shifter LNA PA
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8 Proposed RF BIST for LNA S1 closed: Measure V T1 S2 & S3 closed: Measure V T2
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9 Proposed RF BIST Hardware
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10 Equivalent Circuit Model
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11 Development of Equations (1) (2) (3)
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12 Fault-Free Input Impedance : Voltage gain of Test Amplifier : Voltage gain of BIST
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13 Faulty-Case Input Impedance( V T2 ) : Voltage gain of BIST under faulty case
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14 Fault-Free Voltage Gain : Voltage gain of BIST
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15 Faulty-Case Voltage Gain ( V T1, V T2 ) : Voltage gain of BIST under faulty case
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16 Input Return Loss : Input Return Loss of BIST Fault-Free Case Faulty Case
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17 Output Signal-to-Noise Ratio Faulty Case Fault-Free Case kT: -204 dB B: signal bandwidth
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18 Summary of Equations
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19 5GHz Low Noise Amplifier 0.18 m SiGe HBT Technology
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20 Small-Signal Model for 5GHz LNA Hybrid-π model for HBT with series resistance and two capacitances Inductor model with series resistance Stage 2: same topology as stage 1 Stage 2
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21 RF BIST Circuit Validation Procedure & System Calibration Test V T2 for Gain=3
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22 Programmable Capacitor Banks for C B (D 3 D 2 D 1 ) = (001) for 5.25GHz, (011) for 2.4GHz and (111) for 1.8GHz
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23 Chip Micrograph BIST block TA PD2 PD1
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24 Defect Models Defect Models for Actives
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25 Defect Models Defect Models for Passives
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26 Measurement Set-Up for LNA and TA LNA TA PD1 PD2 S1 S2 V T1 V T2 v in R s =50 Z L Labview Board S3 V L V T
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27 Fault-Free Wafer Level Testing for Catastrophic Faults
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28 Wafer Level Testing for Parametric Variations Tolerance: 20% Good Device Fault Free Device
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29 Results Measured Values mean that external equipment was used. Simulation results are from ADS commercial software. Modeling results are from the Hybrid- and other passives modeling in the LNA circuit.
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30 Input Impedance of TA
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31 Gain of TA
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32 Input Impedances
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33 Gains
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34 Input Return Losses
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35 Input VSWRs
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36 Data Summary ImpedanceGainReturn LossSNR Fault-Free 41.7616.89-20.996.99 Q1 – open base terminal 70.88-44.44-12.939.80 Lb +30% tolerance 49.0114.95-26.796.07
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37 ADC DAC Digital Signal Processor IF Filter RF Filter Power amp. Attenuator RF Filter IF Filter RF Filter Phase filter Amp. PLL VCO Switch RF Filter Antenna SoC Transceiver System Auto Compensation
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Parametric Variations
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39 Capacitor Mirror Banks (CMB) N = 8-bit: When (D 11 D 10 …D 5 D 4 ) = (00…01), C B = C b /8
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40 L c1 Parametric Variations L c1 : Most sensitive component in LNA
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41 Changes of C b1 to Compensate Gain
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42 Gain Compensations L c1 : Most gain-sensitive component in LNA
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43 Noise Figure Compensations
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44 Programmable RF BIST Technique Used for GSM, Bluetooth, IEEE802.11g LNA S1 S2 V T1 V T2 v in R s =50 Z L S3 LNA Under Test v L v T External Board BIST v L1 A/D Labview D N PC CMB
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45 Test Technique Comparison
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46 Limitation
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47 On-going Work Construct automatic test structure with on- chip BIST structure and relays on a load board Develop a LabView software for test automation
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48 Conclusions Introduced a new low-cost RF test hardware. Successful with programmable RF test for different standards. Self-compensation network for process and thermal variations.
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