1. Data-Converter Circuits1

2. sedr42021_0931.jpg
Figure Cascading the small-signal equivalent circuits of the individual stages for the evaluation of the overall voltage gain.
Microelectronic Circuits - Fifth Edition Sedra/Smith

3. sedr42021_0932.jpg
Figure Bode plot for the 741 gain, neglecting nondominant poles.
Microelectronic Circuits - Fifth Edition Sedra/Smith

4. sedr42021_0933.jpg
Figure A simple model for the 741 based on modeling the second stage as an integrator.
Microelectronic Circuits - Fifth Edition Sedra/Smith

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Figure A unity-gain follower with a large step input. Since the output voltage cannot change instantaneously, a large differential voltage appears between the op-amp input terminals.
Microelectronic Circuits - Fifth Edition Sedra/Smith

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Figure Model for the 741 op amp when a large positive differential signal is applied.
Microelectronic Circuits - Fifth Edition Sedra/Smith

7. sedr42021_0936a.jpg
Figure The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit. The switch closes for a small part (t seconds) of every clock period (T). (b) Input signal waveform. (c) Sampling signal (control signal for the switch). (d) Output signal (to be fed to A/D converter).
Microelectronic Circuits - Fifth Edition Sedra/Smith

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Figure The A/D and D/A converters as circuit blocks.
Microelectronic Circuits - Fifth Edition Sedra/Smith

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Figure The analog samples at the output of a D/A converter are usually fed to a sample-and-hold circuit to obtain the staircase waveform shown. This waveform can then be filtered to obtain the smooth waveform, shown in color. The time delay usually introduced by the filter is not shown.
Microelectronic Circuits - Fifth Edition Sedra/Smith

10. sedr42021_0939.jpg
Figure An N-bit D/A converter using a binary-weighted resistive ladder network.
Microelectronic Circuits - Fifth Edition Sedra/Smith

11. sedr42021_0940.jpg
Figure The basic circuit configuration of a DAC utilizing an R-2R ladder network.
Microelectronic Circuits - Fifth Edition Sedra/Smith

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Figure A practical circuit implementation of a DAC utilizing an R-2R ladder network.
Microelectronic Circuits - Fifth Edition Sedra/Smith

13. sedr42021_0942.jpg
Figure Circuit implementation of switch Sm in the DAC of Fig In a BiCMOS technology, Qms and Qmr can be implemented using MOSFETs, thus avoiding the inaccuracy caused by the base current of BJTs.
Microelectronic Circuits - Fifth Edition Sedra/Smith

14. sedr42021_0943.jpg Figure 9.43 A simple feedback-type A/D converter.
Microelectronic Circuits - Fifth Edition Sedra/Smith

15. sedr42021_0944a.jpg
Figure The dual-slope A/D conversion method. Note that vA is assumed to be negative.
Microelectronic Circuits - Fifth Edition Sedra/Smith

16. sedr42021_0944b.jpg Figure 9.44 (Continued)
Microelectronic Circuits - Fifth Edition Sedra/Smith

17. sedr42021_0945.jpg
Figure Parallel, simultaneous, or flash A/D conversion.
Microelectronic Circuits - Fifth Edition Sedra/Smith

18. sedr42021_0946a.jpg
Figure Charge-redistribution A/D converter suitable for CMOS implementation: (a) sample phase, (b) hold phase, and (c) charge-redistribution phase.
Microelectronic Circuits - Fifth Edition Sedra/Smith