1. Simulated Evolution Algorithm for Multi- Objective VLSI Netlist Bi-Partitioning Sadiq M. Sait, Aiman El-Maleh, Raslan Al-Abaji King Fahd University of Petroleum & Minerals Dhahran, Saudi Arabia 27 th May, ISCAS-2003, Bangkok, Thailand

2. 2  Introduction  Problem Formulation  Cost Functions  Proposed Approach  Experimental Results  Conclusion Outline

3. 3 Design Characteristics 0.13M 12MHz 1.5um CAE Systems, Silicon Compilation 7.5M 333MHz 0.25um Cycle-Based Simulation, Formal Verification 3.3M 200MHz 0.6um Top-Down Design, Emulation 1.2M 50MHz 0.8um HDLs, Synthesis 0.06M 2MHz 6um SPICE Simulation Key CAD Capabilities The challenges to sustain such a fast growth to achieve giga-scale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology. New issues have also come up. VLSI Technology Trends

4. 4 1.System Specification 2.Functional Design 3.Logic Design 4.Circuit Design 5.Physical Design 6.Design Verification 7.Fabrication 8.Packaging Testing and Debugging VLSI design process comprises a number of levels: VLSI Design Cycle

5. 5 What is Physical Design? A process that translates a structural (netlist)  description into a geometric description that is used to manufacture a chip. The physical design cycle consists of: 1.Partitioning 2.Floorplanning and Placement 3.Routing 4.Compaction Why do we need Partitioning ? Physical Design

6. 6 System Level Partitioning Board Level Partitioning Chip Level Partitioning System PCBs Chips Subcircuits /Blocks Levels of Partitioning

7. 7 Partitioning Algorithms Group MigrationIterative Heuristics Performance Driven 1.Kernighan-Lin 2.Fiduccia- Mattheyeses (FM) 3.Multilevel K-way Partitioning Others 1.Simulated Annealing 2.Simulated Evolution 3.Tabu Search 4.Genetic Algorithm 1.Lawler et al. 2.Vaishnav 3.Choi et al. 4.Jun’ichiro et al. 1.Spectral 2.Multilevel Spectral Classification of Partitioning Algorithms

8. 8 Related previous Work 1969A bottom-up approach for delay optimization (clustering) was proposed by Lawler et al. 1998A circuit partitioning algorithm under path delay constraint is proposed by jun’ichiro et al. The proposed algorithm consists of the clustering and iterative improvement phases. 1999Two low power oriented techniques based on simulated annealing (SA) algorithm by choi et al. 1999Enumerative partitioning algorithm targeting low power were proposed by Vaishnav et al. Enumerates alternate partitioning and selects a partitioning that has the same delay but less power dissipation.

9. 9 Need for Power optimization:  Portable devices  Power consumption is a hindrance to further integration  Increasing clock frequency Need for Delay optimization:  In current sub micron design wire delays tend to dominate gate delay.  Larger die size imply long on-chip wires which affect performance  Delay due to off-chip capacitance Objectives: Power, Delay & Cutset are optimized Constraint: Balanced partitions (with some tolerance) Motivation & Objective

10. 10 Problem formulation The circuit is modeled as a hypergraph H(V,E), where V={v 1,v 2,v 3,… v n } is a set of modules (cells) And E={e 1, e 2, e 3,… e k } is a set of hyperedges. Being the set of signal nets, each net is a subset of V containing the modules that the net connects. A 2-way partitioning of a set of nodes V is to determine subsets V A and V B such that V A  V B = V and V A  V B = 

11. 11  Based on hypergraph model H = (V, E)  Cost: c(e) = 1 if e spans more than 1 block  Cutset = sum of hyperedge costs  Efficient gain computation and update cutset = 3 Cutset

12. 12 path  : SE 1  C 1  C 4  C 5  SE 2. Delay  = CD SE1 + CD C1 + CD C4 + CD C5 + CD SE2 CD C1 = BD C1 + LF C1 * ( Coffchip + CINP C2 + CINP C3 + CINP C4 ) Delay

13. 13 The average dynamic power consumed by CMOS logic gate in a synchronous circuit is given by: Ni is the number of output gate transition per cycle (Switching Probability) load capacitance = Load Capacitances before Partitioning + load due to off chip capacitance Power Total Power dissipation of a Circuit:

14. 14 Weighted Sum Approach 1.Problems in choosing weights 2.Need to tune for every circuit Unifying Objectives by Fuzzy logic  Imprecise values of the objectives  Best represented by linguistic terms that are basis of fuzzy algebra  Conflicting objectives  Operators for aggregating function

15. 15 1.The cost to membership mapping 2.Linguistic fuzzy rule for combining the membership values in an aggregating function 3.Translation of the linguistic rule in form of appropriate fuzzy operators 4.Fuzzy operators And-like operators: Min operator  = min (  1,  2) And-like OWA:  =  * min (  1,  2) + ½ (1-  ) (  1+  2) Or-like operators: Max operator  = max (  1,  2) Or-like OWA:  =  * max (  1,  2) + ½ (1-  ) (  1+  2) Where  is a constant in range [0,1] Fuzzy logic for Multi-objective function

16. 16 WhereO i and C i are lower bound and actual cost of objective “i”  i (x) is the membership of solution x in set “good ‘i’ g i is the relative acceptance limit for each objective. Membership functions

17. 17 A good partitioning can be described by the following fuzzy rule IF solution has small cutset AND low power AND short delay AND good Balance THEN it is a good solution The above rule is translated to AND-like OWA Fuzzy linguistic rule & Cost function Represent the total Fuzzy fitness of the solution, our aim is to Maximize this fitness Respectively (Cutset, Power, Delay, Balance) Fitness

18. 18 Simulated Evolution Algorithm Simulated_Evolution Begin Start with an initial feasible Partition S Repeat Evaluation : Evaluate G i (goodness) for all modules Selection : For each V i (cell) DO begin if Random Rm > G i then select the cell End For Allocation : For each selected V i (cell) DO begin Move the cell to destination block. End For Until Stopping criteria is satisfied. Return best solution. End

19. 19 Cut goodness d i : set of all nets, connected and not cut. w i : set of all nets, connected and cut.

20. 20 Power Goodness V i is the set of all nets connected and Ui is the set of all nets connected and cut.

21. 21 Delay Goodness Ki: is the set of cells in all paths passing by cell i. Li: is the set of cells in all paths passing by cell i and are not in same block as i.

22. 22 Final selection Fuzzy rule IF cell ‘i’ is near its optimal cut-set goodness as compared to other cells AND AND THEN it has a high goodness. near its optimal net delay goodness as compared to other cells OR T (max) (i) is much smaller than T max near its optimal power goodness compared to other cells

23. 23 Experimental Results ISCAS 85-89 Benchmark Circuits

24. 24 SimE versus Tabu Search & GA against time Circuit: s13207

25. 25 Experimental Results: SimE versus TS and GA SimE results were better than TS and GA, with faster execution time.

26. 26 Conclusion The present work addressed the issue of partitioning VLSI circuits with the objective of reducing power and delay (in addition to nets cut) Fuzzy logic was resorted to for combining multi- objectives Iterative algorithms (GA, SA, and SimE) were investigated and compared for performance in terms of quality of solution and run time SimE outperformed TS and GA in terms of quality of solution and execution time

27. 27 Thank you

28. 28 T max :delay of most critical path in current iteration. T (max) (i) :delay of longest path traversing cell i. X path = T max / T (max) (i) Fuzzy Goodness Respectively (Cutset, Power, Delay ) goodness.