1. Pipelined Parallel AC-based Approach for Multi-String Matching Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C. Authors: Wei Lin, Bin Liu Publisher: 2008 14th IEEE International Conference on Parallel and Distributed Systems.IEEE Computer Society Present: Chia-Ming,Chang Date: 2, 3, 2009 1

2. Outline 1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion 2

3. Introduction (1/3) A string Y of length n is a sequence of characters c 1 c 2 ……c n. Let Σ = {Y 1, Y 2,...Y N } be a finite set of strings called keywords or signatures proposed hardware solutions are based on the well-known Aho-Corasick (AC) algorithm, where the system is modeled as a deterministic finite automaton(DFA) we present a pipelined processing approach to the implementation of AC algorithm, called P2- AC. 3

4. Introduction (2/3) 4

5. Introduction (3/3) 5

6. Outline 1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion 6

7. Pipelined Architecture (1/7) 7

8. Pipelined Architecture (2/7) 8 pattern set is {apple, applause, ampliation, past, pat, parable} appl e appl ause ampl iati on past pat para ble

9. Pipelined Architecture (3/7) 9

10. Pipelined Architecture (4/7) 10

11. Pipelined Architecture (5/7) 11

12. Pipelined Architecture (6/7) 12 7 1 2 3 5 6 4 0

13. Pipelined Architecture (7/7) 13, T1 T2 T3 T4 4*n+14*n+24*n+34*n

14. Outline 1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion 14

15. Conclusion (1/4) In all, the Snort pattern set costs 305 M 512 SRAM blocks and 228 M 4K SRAM blocks, which are about 133KB and 13.68 bits per character for the utilized Snort pattern set. which are 4132 LUTs in FPGA and about 0.05 LUTs per character. We use Altera’s StratixII EP2S60 FPGA to implement the pattern matching system using P2-AC method. 15

16. Performance evaluation (2/4) 16

17. Performance evaluation (3/4) 17

18. Performance evaluation (4/4) 18

19. Outline 1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion 19

20. Conclusion (1/1) The memory cost of P2-AC is as low as 13.68 bits/char for a signature set with 5.7K strings which is less than 47% of the best known AC-based methods. Speed 2(char/cycle) Using the Xilinx Virtex-5 FPGA that operates at 550 MHz, the throughput of P-AC is up to 8.8 Gbps. 20