Presentation is loading. Please wait.

Presentation is loading. Please wait.

Proposal for an FP6 STREP FET based on nanodevice ideas with SiC.

Similar presentations


Presentation on theme: "Proposal for an FP6 STREP FET based on nanodevice ideas with SiC."— Presentation transcript:

1 Proposal for an FP6 STREP FET based on nanodevice ideas with SiC

2 Information Society Technologies 2003-2004 Workprogramme 2/3 of the budget will be devoted to IPs and NoEs. HOWEVER On average two to three IPs and NoEs are expected to be supported for each Strategic Objectiv. The IST thematic priority will also support Specific Targeted Research Projects (STREPs) several STREPs are also foreseen in most objectives. IST will support research into future visions and emerging technologies (FET). All instruments should have adequate industrial participation. The selection criteria and weights and thresholds for the FET open scheme are different. Scientific and technological excellence, Potential impact,Quality of the consortium

3 The Community support for IST in FP6 will help mobilise the industrial and research community around high-risk long term goals. 2.3.1.2 Micro and nano systems Additional STREPs will be restricted to explore highly promising alternative approaches to prepare new technological fields to explore the application potential of micro-nano technology Nano-devices with SiC Ideas of a theorist:

4 SUBSTRATE: Si (100); P- or N-doped (4-6  cm). OXIDE: 100 nm, thermally grown at 1050 °C in dry oxygen, Quality: density of electrically active states in the oxide and at the interface < 5·10 10 cm -2 (CV) TREATMENT: furnace anneal in Ar gas flow of 100 cm 3 /min, containing 5 % CO (gas purity: 99.995%) - for 3, 8 and 20 hours - between 900-1190  C Characterization of samples by: SIMS, XPS, TEM, AFM, ESR, CV Heat treatment of a SiO 2 /Si system of electronic quality in a CO containing gas: CO diffusion  dissociation  SiC formation at SiO 2 /Si interface. 1. EXPERIMENT

5 SiC is present in form of cubic crystallites at the interface: 3 hours20 hours 45  45  20 nm 90  90  35 nm ratio of average grain volumes: 7 (reaction limited growth) nucleation density, 2.5  10 9 cm -2, independent of time

6 About 90 % of the crystallites are epitaxially oriented: Orientation of the grains: (001)Si || (001)SiC [110]Si || [110]SiC Top viewSide view

7 There are no voids at the Si/SiO 2 interface!

8 SiC ESR: dangling bond density ~ 4  10 12 cm -2 (courtesy of M. Brandt, TU-Munich) 4 : 5 fit between lattice constants:

9 LIKELY GROWTH MECHANISM 1.(CO) + 2  loss of ~ 7 eV/CO (K  et al. PRB 2001) 2.2 (CO) + 2  2 + 3(O 2 ) loss of ~ 8 eV/CO ;  V=-63 Å 3 3.4(CO) + 6  4 + 2 gain of ~ 6 eV/CO ;  V=+48 Å 3

10 AFM after etching off the SiO 2 layer shows etch pits at the Si/SiC interface: Together with lateral growth direction and shape of the cross section, proof for CO dissociation at the Si/SiC interface!

11 GRAINS COALESCENCE WITHOUT GRAIN BOUNDARY

12 SiO 2 Si (SOI) SiO 2 Si SiC IDEA 1.a Band structure: V C

13 Problems to be solved (before thinking of devices) 1.Lateral growth rate: depends only on [CO] and T - growth volume is linear with time - T (> 1000 C) is critical - Rate with 1.00 atm CO 2 at 1190 C is the same as with 0.05 atm CO but quality somewhat worse 2. Control of nucleation: presently random - density independent of process parameters: ~ 2.5 ·10 9 cm -2 - suspicion: depends on defects at interface (irradiation in pattern?) 3. During long anneals the oxide degrades 4. Passivation of dangling bonds: - dangling bond density corresponds to 4:5 lattice parameter ratio - “wet” treatments had no effect

14 SiO 2 Si SiC IDEA 1.b Band structure: V C

15 IDEA 1.+ (on the side) Nucleation process for 3C-SiC heteroepitaxy

16 2. EXPERIMENT ALE of SiC: -monolayer growth of 3C-SiC on Si in ALE proven [Hara et al. Thin Solid Films 225, 240 (1993)] -monocrystalline growth was possible even on Si in a commercial planetary reactor [Sumakeris et al., ibid. p. 219; Nagasawa & Yamaguchi, ibid. p.230] -layer by layer 3C- SiC homoepitaxy in ALE demonstrated [Fuyuki et al., ibid. p. 225]

17 Calculation of the stability and electronic structure of various extended defects in SiC: alternating layer sequences in SiC. 2. THEORY Based on bulk band off-sets, strong QW effect expected. No stress in the system!

18 Methods: ab initio DFT electronic structure calculations; DFTB-MD - DFTB-MD: if the “homo-double-layers” are formed during ALE, they are stable up to temperatures where surface H is released Studies regarding stability during growth (attack of single CH 3 on Si-C-Si-Si-H and of SiH 3 on C-Si-C-C-H sequence) are under way.

19 - ab initio DFT: to keep periodicity, both type of “homo-double- layers” have to be built in into the supercell. Further possibilities…to be examined by calculations 2.9 eV Wave function at the VB edge: (LDA problem with CB)

20 Admittedly: it is a long shot before thinking of devices but IST will support research into future visions (FET) and FP6 will help mobilise around high-risk long term goals. So, while theory is working: - why not study ways to use such systems - why not study problems of contacting, integrating, etc. - why no try to grow it with ALE!?!? Device ideas????? HEMT ? Idea on the side: blocking of stacking fault motion in SiC!

21 Possible distribution of tasks


Download ppt "Proposal for an FP6 STREP FET based on nanodevice ideas with SiC."

Similar presentations


Ads by Google