1. Synchronous Digital Design Methodology and Guidelines
Digital System Design

2. Synchronous Design All flip-flops clocked by one common clock
Reset only used for initialization
Races and hazards are no problem

3. Why synchronous design?
Hazard
Race
Problems due to timing that cannot be observed from functional analysis

4. Timing Hazard
Static hazard: possibility of a brief signal value change when the signal was expected to be stable, due to timing (glitch)
Dynamic hazard: possibility of multiple output transitions caused by a single input transition due to multiple signal paths with different delays

5. Static Hazard
If d is the delay of each gate

6. Analyzing Static Hazards using Karnaugh maps
A static hazard can occur when changing a single input variable causes a jump from one prime implicant to another
Solution: include an additional prime implicant

7. Eliminating hazards using Flip-Flops

8. Synchronous Design Three things must be ensured by the designer:
Minimize and determine clock skew
Account for flip-flop setup and hold times
Reliably synchronize asynchronous inputs

9. Timing Analysis
>0 Setup time margin
>0 Hold time margin

10. Example
The circuit of Figure 1 is synthesized to a gate-level netlist. What is the estimated maximum operating frequency for the circuit, assuming:
A flip-flop setup-time requirement of 0.8 ns,
A flip-flop hold-time requirement of 0.2 ns,
A flip-flop propagation delay of 1 ns,
A comb1 (combinational) block delay of 6 ns
A comb2 block delay of 10 ns
A comb3 block delay of 5 ns
A comb4 block delay of 4 ns
A comb5 block delay of 2 ns

11. Clock skew

12. Example
Determine the maximum frequency of the following circuit with and without skew

13. Clock Jitter

14. Clock Gating
Clock gating is done to disable the clock for low power consumption using a clken signal
It is wrong to gate the clock in the following way, instead use a synchronous load (enable) signal

15. Asynchronous Inputs
It is impossible to guarantee setup and hold timing constraints on inputs synchronized with a clock unrelated to the system clock

16. Asynchronous inputs
Synchronize only in one place

18. Metastability
Metastability is a phenomenon that may occur if the setup and hold time requirements of the FF are not met, leading in the output settling in an unknown value after unspecified time.

19. Reliable synchronizer design

20. Example
Design a synchronizer that synchronizes two inputs async1 and async2 generated with a 50 MHz clock CLK1, to a system with a 33 MHz clock CLK2 totally independent of CLK1. Draw appropriate timing diagrams.

21. Mean-time between failures
f: frequency of flip-flop clock
a: number of asynchronous input changes per second in flip-flop input
To, τ: constants depending on flip-flop electrical characteristics
Assume a 10 Mhz clock, ts = 20 ns, To = 0.4 sec, τ = 1.5 ns and that the asynchronous input can change 100,000 times per second, then
tr = 1/f – ts = 80 ns
MTBF(80ns) = exp(80/1.5)/0.4×10^7×10^5= 3.6×10^11 s

22. Cascaded synchronizer

23. Synchronizing bus transfers
Do not use dual f/f synchronizers in all bits, this will only increase the chances of metastability
Synchronize the control signals and read the input when safe to do so

24. Synchronization circuit

25. FIFO Synchronizer basic concept
On burst transfers, the receiver cannot afford to wait for the signal to settle.
Solution: A dual-port RAM FIFO
Problem: How do we synchronize the counters?

26. Summary
In order to avoid hazards and races, synchronous design is used
In synchronous design a single common clock is used and reset is only used for initialization
The only considerations in synchronous design are the flip-flop setup and hold times, clock skew and asynchronous input synchronization
Asynchronous inputs are commonly synchronized using 2 flip-flops clocked with the synchronous system clock
Synchronization should only be done in one place
In bus transfers, synchronize only the control signals or use a FIFO

27. Design trade-offs

28. Common design trade-offs
Performance
Latency
Throughput
Delay (timing)
Area
Gates (ASIC)
Flip-flops/LUTs (FPGA)
Power consumption
Dynamic
Static
Leakage

29. Design for Speed Design for High Throughput Design for Low Latency
Definition: High data rate, acceptable latency
Technique: Pipelining
Design for Low Latency
Definition: Output available as soon as possible
Technique: Parallelism, Removal of pipelining
Design for Timing
Definition: High clock speed, low delay between registers
Technique: Add intermediate registers

30. Example 1: Design for low latency (parallelism)
X = a + b + c + d
Delay = 3*add Delay = 2*add
Latency = 1 cycle Latency = 1 cycle
Throughput = X bits/clock Throughput = X bits/clock

31. Example 1: Design for delay
X = a + b + c + d
Delay = 1*add + Reg
Latency = 2 cycles
Throughput = X bits/clock

32. Example 2: Design for delay
for (i=0; i<4; i++)
x+= a[i]*b;
Delay: 1*Mul + 1 Add
Latency: 4 cycles
Throughput: X bits/4 cycles

33. Example 2: Design for latency

34. Example 2: Design for throughput

35. Design for Area
Resource (logic) sharing
Rolling up the pipeline

36. Resource Sharing Y= C1* X[0] + C2 *X[1] + C3*X[2]
Is it possible to perform all multiplications with a single multiplier?
Is it possible to perform all additions with a single accumulator?

37. Resource Sharing

38. Design for low-power Power components:
Dynamic power consumption (switching): power consumed due to charging and discharging parasitic capacitances on gates and wires
Static power consumption: Power consumed when no switching
Leakage current power consumption:

39. Design for power Clock Gating Dual-edge triggered Flip-Flops
Lowering core voltage

40. Clock Gating
Clock gating is done to disable the clock for low power consumption using a clken signal
It is wrong to gate the clock in the following way, instead use a synchronous load (enable) signal or a global clock multiplexer (if available)

41. Dual-Edge Triggered Flip-Flops
Single-edge triggered FF
Dual-edge triggered FF (same data rate)
Dual-edge triggered flip-flops should only be used if available in the target technology
Otherwise, redundant flip-flops and gating will be used to emulate the desired functionality

42. Lowering core voltage
Only reduce core voltage within acceptable limits (5 to 10%)
Power consumption in a simple resistor is proportional to the square of the voltage
Keep in mind that performance will degrade too

43. Review questions/problems
Pipelining will make your circuit
A. smaller
B. exhibit lower latency
C. Consume less power
D. exhibit higher throughput
Parallelism creates a
A. latency/throughput trade-off
B. Performance/area trade-off
C. Area/power consumption trade-off
D. performance/power consumption trade-off
Pipeline the following datapath for a three-cycle latency so that you get the maximum operation frequency. How much is the maximum operation frequency?