1. 1 Seoul National University Introduction

2. 2 Why do you want to study Computer Architecture? Because….You won’t graduate if you don’t take this course. Because….You want to design the next great instruction set.  Instruction set architecture has largely converged, especially in the desktop/server/laptop space.  Dictated by powerful market forces (Intel/ARM). Because….You want to become a computer architect and design the next great computer systems. Because….The design, analysis, implementation concepts that you will learn are vital to all aspects of computer science and engineering – operating systems, computer networks, compiler, programming languages Because….The course will equip you with an intellectual toolbox for dealing with a host of systems design challenges From Prof. Fernando C. Colon Osorio’s lecture notes Seoul National University

3. 3 Course Goals To understand  Interfaces  Instruction Set Architecture (ISA) – The Hardware/Software Interface  Engineering methodology / Correctness criteria / Evaluation methods / Technology trends involved in  Processor  Cache memory  Virtual memory  I/O system Seoul National University

4. 4 Interface Source : http://www.webster.com Seoul National University

5. 5 Abstract Data Type (ADT) as an Example of Interface Abstract data type : A set of data values (state) and associated operations that are precisely specified independent of any particular implementation ADT Example : stack push is_empty pop ·· stack S (top) (bottom) Create_stack Destroy_stack Seoul National University

6. 6 Abstract Data Type (ADT) as an Example of Interface Operations viewed as state transformation 2 1 5 S (Before) stack 2 1 5 S` 4 (After) stack Push (s, 4) Seoul National University

7. 7 Abstraction Before After Jeff Kramer, “Is Abstraction the Key to Computing,” Communications of ACM, April 2007, Vol. 50, No. 4, pp. 37 - 42. Seoul National University

8. 8 Abstraction Before After Seoul National University

9. 9 Abstraction Before After Jinwook Seo, “Information Visualization Design for Map Use on Future Mobile Devices (Presentation at Samsung Electronics, Dec. 8, 2008) Seoul National University

10. 10 Instruction Set Architecture (ISA) assembler complier Operating System library ISA S/W H/W Application Seoul National University

11. 11 Instruction Set Architecture as an ADT “…the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure (state) and functional behavior (operations), as distinct from the organization of the data flow and controls, the logical design, and the physical implementation.” - Amdahl, Blaauw, and Brooks, 1964 Seoul National University

12. 12 Instruction Set Architecture as an ADT Before Register and Memory add r 1, r 2, r 3 20 2 1 r3r3 12 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 2 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) After Register and Memory Registers Memory 21 2 20 r3r3 12 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 2 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Seoul National University

13. 13 Instruction Set Architecture as an ADT Before Register and Memory lw r 2, 1(r 0 ) After Register and Memory 22 2 20 r3r3 7 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 2 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory 21 2 20 r3r3 12 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 2 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Seoul National University

14. 14 Instruction Set Architecture as an ADT Before Register and Memory sw r 3, 0(r 0 ) After Register and Memory 23 2 20 r3r3 7 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 8 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory 22 2 20 r3r3 7 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 2 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Seoul National University

15. 15 Instruction Set Architecture as an ADT Before Register and Memory beq r 0, r 1, 2 After Register and Memory 24 2 20 r3r3 7 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 8 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory 23 2 20 r3r3 7 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 8 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Seoul National University

16. 16 Instruction Set Architecture as an ADT Before Register and Memory j 15 After Register and Memory 15 0 20 r3r3 7 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 8 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory 24 0 20 r3r3 7 8 r2r2 r1r1 r0r0 PC 63 24 23 22 0 8 7 4 0 2 1 3 ·· 20 21 ·· (add r 1, r 2, r 3 ) (lw r 2, 1(r 0 )) (sw r 3, 0(r 0 )) (beq r 0, r 1, 2) (j 15) Registers Memory Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Seoul National University

17. 17 Design Techniques For Each Design Technique  Engineering methodology  Correctness criteria  Evaluation methods  Technology trends Seoul National University

18. 18 Design Techniques Processor I-cache Unified cache D-cache Processor Memory Hierarchy Input/Output and Storage To main memory / I/O Systems Sequential implementation Pipelined implementation Out of order execution Speculative execution Cache Memory Virtual Memory Seoul National University

19. 19 Engineering methodology Rule 1 : Identify and optimize the common case Rule 2 : Make the rare case correct and reasonably fast Seoul National University

20. 20 Correctness criteria Examples  Pipelined execution : pipelined execution of instructions is correct if the results is as if the instructions were executed sequentially  Cache memory : execution of instructions on a system with cache memory is correct if the results is as if the instructions were executed on the same system but without cache memory  We’ll see a lot of as if’s Seoul National University

21. 21 Performance Evaluation Methods Performance types  Time  response time  execution time  Rate  throughput : MIPS, MFLOPS  bandwidth : Mbps  Ratio  relative performance (both time and rate) Seoul National University

22. 22 Technology Trends Transistors Per Die Trends Processor Performance Trends  Processor Computations/Energy Trends  Processor Clock Rate/Power Trends DRAM Technology Trends Hard Disk Drive (HDD) Technology Trends Flash Memory Technology Trends Seoul National University

23. 23 Transistors Per Die Trends Source: www.icknowledge.com Seoul National University

24. 24 Processor Performance Trends Seoul National University David A. Patterson and John L. Hennessy. “Computer Organization and Design, Fourth Edition: The Hardware/Software Interface” Morgan Kaufmann Publishers, 2009.

25. 25 Processor Computations/Energy Trends J. G. Koomey, et al. “Outperforming Moore’s Law” IEEE Spectrum, Vol. 47, No. 3, Mar. 2010, pp. 68 – 68. Seoul National University

26. 26 Processor Clock Rate/Power Trends S. H. Fuller and L. I. Millett. “Computing Performance: Game Over or Next Level” IEEE Computer, Vol. 44, No. 1, Jan. 2011, pp. 31 – 38. Seoul National University David A. Patterson and John L. Hennessy. “Computer Organization and Design, Fourth Edition: The Hardware/Software Interface” Morgan Kaufmann Publishers, 2009.

27. 27 DRAM Technology Trends year size cycle time 198064 Kbits 250 ns 1983256 Kbits 220 ns 19861 Mbits 190 ns 19894 Mbits 165 ns 199216 Mbits 145 ns 1996 64 Mbits 125 ns 2000 256 Mbits 100 ns (4x in three years) 60% increase/year (4x in four years) Seoul National University David A. Patterson and John L. Hennessy. “Computer Organization and Design, Fourth Edition: The Hardware/Software Interface” Morgan Kaufmann Publishers, 2009.

28. 28 Hard Disk Drive (HDD) Technology Trends Disk density: 1.50x - 1.60x per year (4x in three years) E. Grochowski and R. E. Fontana, Jr., “An Analysis of Flash and HDD Technology Trends,” Flash Memory Summit 2011. Seoul National University

29. 29 Flash Memory Technology Trends S. Deutsch, “Bringing Solid State Drives to Mainstream Notebooks,” Flash Memory Summit 2007. P. Ranganathan. “From Microprocessors to Nanostores: Rethinking Data-Centric Systems,” IEEE Computer, Vol. 44, No. 1, Jan. 2011, pp. 39 – 48. Seoul National University

30. 30 Pitfalls of Computer Technology Forecasting DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more.” Microsoft, 1980 “640K ought to be enough for anybody.” Bill Gates, 1981 “Computers in the future may weigh no more than 1.5 tons.” Popular Mechanics “I think there is a world market for maybe five computers.” Thomas Watson, IBM Chairman, 1943 “There is no reason anyone would want a computer in their home.” Ken Olsen, DEC founder, 1977 “The 32-bit machine would be an overkill for a personal computer.” Sol Libes, ByteLines From Prof. Behrooz Parhami’s lecture notes Seoul National University