1. RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FPL September 5-7, 2011

2. Why Build Your Own Tools Anyway? Proof of concept in their own right –Hypothetical architectures may not account for all real-world factors Targeting real chips important The field needs wild and crazy ideas –The vendors don’t have all the answers! That requires custom CAD tools 2

3. The Challenge Building custom physical CAD Tools for commercial FPGAs == difficult –Closed, proprietary device databases –Unsupported interfaces Architectural nuances complicate things… 3

4. Motivation #1: Rapid Prototyping tool runtime quality of result (QOR) hours minutes seconds

5. Motivation #1: Rapid Prototyping tool runtime quality of result (QOR) hours minutes seconds Commercial tools focus here…

6. Motivation #1: Rapid Prototyping tool runtime quality of result (QOR) hours minutes seconds Commercial tools focus here… For rapid prototyping and implementation we would like tools which focus here…

7. Motivation #2: Reliability SEU mitigation using TMR –Selective duplication tools –Single-bit TMR failures in routing Half-latch detection –Weak keeper tie-offs susceptible to SEUs Need a way to do post-PAR analysis Need a way to do post-PAR modifications 7

8. XDL: A Physical Database for Xilinx A textual design database representation –For Xilinx designs Available for many years 8 Custom CAD Tools

9. #1: XDL as a Design Representation 9 xdl –ncd2xdl design –Converts NCD to XDL xdl –xdl2ncd design –Converts XDL back to NCD Can inject own CAD tools at any point in the flow or bypass it entirely Must convert back to NCD for bitgen Custom CAD Tools

10. #2: XDLRC as a Device Description xdl -report -pips -all_conns partName –Dumps textual description of specific device as a.xdlrc file –Details everything you need to write placers and routers (except timing data) 10

11. Challenges of XDLRC Device Descriptions They are massive! –Up to 73GB of text for one device! –Difficult for tools to directly operate on XDLRC They are missing some information –Primitive sites that support more than 1 type –Pin name mappings missing for some sites –Result: placement/routing inefficiencies occur RapidSmith solves these problems 11

12. SOME TERMINOLOGY 12

13. A Familiar View of the Fabric… 13

14. A Familiar View of the Fabric… 14

15. A Familiar View of the Fabric… 15 L_TERM INT L_TERM INT L_TERM INT INT_SO INT CLB IOIS

16. XDLRC Abstraction – 2D Tile Array 16

17. XDLRC Abstraction - Tiles 17 HCLK_X1Y39 INT_X2Y37 CLB_X2Y37 DSP_X10Y32 BRAM_X5Y32

18. XDLRC Abstraction – Primitive Sites 18 INT_X2Y37 Contains: TIEOFF_X2Y37 CLB_X2Y37 Contains: SLICE_X3Y75 SLICE_X3Y74 SLICE_X2Y75 SLICE_X2Y74 BRAM_X5Y32 Contains: RAMB16_X0Y8 FIFO16_X0Y8 DSP_X10Y32 Contains: DSP48_X0Y17 DSP48_X0Y16

19. XDL EXAMPLES 19

20. XDL Example 20 inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91, cfg " BXINV::BX BYINV::#OFF... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4))... YUSED::#OFF ";... net "shiftResult4", cfg " ", inpin "inst4" G3, outpin "inst5" YQ, ;

21. XDL Example 21 inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91, cfg " BXINV::BX BYINV::#OFF... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4))... YUSED::#OFF ";... net "shiftResult4", cfg " ", inpin "inst4" G3, outpin "inst5" YQ, pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2, pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT, pip INT_X31Y53 OMUX_S3 -> IMUX_B18, pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3, ;

22. XDL Module Example 22 module "mux" "inst23", cfg " _SYSTEM_MACRO::FALSE "; port "mux5i_0_inport" "inst31" "F4"; port "mux5i_1_inport" "inst33" "F2";... inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91, cfg " BXINV::BX BYINV::#OFF... YUSED::#OFF ";... net "shiftResult4", cfg " ", inpin "inst4" G3, outpin "inst5" YQ, pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2, pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT, pip INT_X31Y53 OMUX_S3 -> IMUX_B18, pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3, ; endmodule "mux";

23. THE RAPIDSMITH TOOL SUITE 23

24. RapidSmith 24 XDL File RapidSmith XDL File

25. RapidSmith 25 XDL File RapidSmith XDL File Internal Graph Represenation Java API

26. RapidSmith 26 XDL File RapidSmith XDL File Java API Internal Graph Represenation Custom Cad Tools ( create, place, route, modify circuits ) Custom Cad Tools ( create, place, route, modify circuits )

27. What is RapidSmith? Manipulates XDL/XDLRC Framework for FPGA CAD tools Written in Java Creates compact database files for Xilinx devices Includes missing XDLRC data Tools, examples, documentation Open source download at: –http://rapidsmith.sourceforge.nethttp://rapidsmith.sourceforge.net 27

28. RapidSmith Abstractions 28 Design Instance PrimitiveType Attribute (List) PrimitiveSite Net NetType Pin (List) PIP (List) Module Port (List) Instance (List) Net (List) ModuleInstance Instance (List) Net (List Device Tile (2D Array) TileType PrimitiveSite (Array) PrimitiveType Tile Wire XDL XDLRC

29. XDLRC Device File Creation Three major strategies to reduce XDLRC information size: –Aggressive wire and object reuse –Careful pruning of unnecessary wires –Customized serialization and compression XDLRC size compression of >10,000X Device files load in just a few seconds or less 29

30. RapidSmith Device Files Performance 30 Xilinx Part Name XDLRC Report Size RapidSmith File Size Memory Footprint Load Time From Disk Virtex 4 LX20010.0 GB1.01 MB61 MB602 ms Virtex 5 LX33012.5 GB1.07 MB69 MB622 ms Virtex 6 CX240T8.5 GB0.94 MB35 MB460 ms Virtex 6 LX76022.8 GB1.76 MB77 MB1.07 s Virtex 7 855T32.0 GB2.63 MB115 MB1.41 s Virtex 7 2000T73.6 GB5.96 MB301 MB3.34 s

31. 7 EXAMPLES OF RAPIDSMITH USE AND CAPABILITIES 31

32. RapidSmith Example #1: Random Placer 32 public class RandomPlacer{ public static void main(String[] args){ // Create and load a design Design design = new Design(args[0]); Random rng = new Random(0); // Create random number generator // Place all unplaced instances for(Instance i : design.getInstances()){ if(i.isPlaced()) continue; PrimitiveSite[] sites = design.getDevice().getAllCompatibleSites(i.getType()); int idx = rng.nextInt(sites.length); int watchDog = 0; // Find a free primitive site while(design.isPrimitiveSiteUsed(sites[idx])){ if(++idx > sites.length) idx = 0; if(++watchDog > sites.length) System.out.println("Placement failed."); } i.place(sites[idx]); } // Save the placed design design.saveXDLFile(args[1]); } }

33. RapidSmith Example #2: Placing a Module 33 // Load XDL file (parses XDL, populated design object) Design design = new Design("moduleContainingDesign.xdl"); // Get the 1024-FFT module definition by name Module fft = design.getModule("fft1024"); // Create an instance of the FFT module called "f0" ModuleInstance mi = design.createModuleInstance("f0", fft); //Find all compatible sites with the anchor PrimitiveType type = mi.getAnchor().getType(); PrimitiveSite[] sites = design.getDevice().getAllCompatibleSites(type); int i = 0; while(!mi.place(sites[i++], design.getDevice())){ if(i >= sites.length) error(mi.getName()+ " has no valid placement!"); }

34. RapidSmith Example #3: VCC/GND Handling GND/VCC supplied in two ways: –LUTs configured to drive ‘1’ or ‘0’ –TIEOFF primitives in every switch box Supplied GND / VCC posts Router must partition nets into neighborhoods to use local static sources –RapidSmith includes a StaticSourceHandler class with a variety of methods to provide this functionality 34

35. RapidSmith Example #4: HMFlow 35.mdl HM Cache Generic HMG Design Parser & Mapper Design Stitcher XDL Hard Macro Placer XDL Router.xdl I NPUT D ESIGNS H ARD M ACRO S OURCES P LACED & R OUTED XDL Rapid compilation approach using hard macros Built on top of RapidSmith Part of CHREC research project Demonstrated > 50X reduction in tool flow time

36. RapidSmith Example #5: Device Browser 36

37. RapidSmith Example #6: Design Explorer 37

38. RapidSmith Example #7: Custom Hard Macro Placer 38

39. 39 RapidSmith Example #7: Timing Visualizer

40. Conclusion RapidSmith –Provides XDL-based infrastructure –Designed to aid in the construction of custom CAD tools Flexible –Custom CAD flow HMFlow for Hard Macro-Based Design –Custom individual steps in the flow Placer or router –Post Xilinx flow circuit modifications Reliability modifications –Post Xilinx flow circuit analysis Timing visualization Available open source: –http://rapidsmith.sourceforge.nethttp://rapidsmith.sourceforge.net 40