Getting Started with MPC560xB The Freescale Cup

Getting Started with MPC560xB The Freescale Cup
Steve Mihalik January 24, 2011

Agenda – Getting Started with MPC560xB
Time Topic Slide # Exercise 9:00 Overview 3 9:10 System Integration Unit – Pads, Simple I/O 11 9:20 Clocks 20 - Reference: Clock Management Unit 28 9:30 RUN Modes 34 PLL init, Mode Entry, Toggle Pin 10:00 Timed I/O – PWM, Counter, Input Capture 44 PWM & Counter 10:30 - Break - 10:45 Interrupts – 1 msec Task Scheduler 64 INTC & PIT 11:15 Analog to Digital Conversions (ADC) 73 ADC 11:45 Direct Memory Access (DMA) 86 Noon 12:15 Camera Interface 12:40 Motor Interface

MPC560xB MPC5607B Overview

Communications I/O System
MPC5607B (1.5MB Flash) System Integration Crossbar Masters Debug CORE Power Architecture e200z0 core running at Ta=105C (48Mhz at 85oC Base) VLE ISA instruction set for superior code density Memory Protection Unit with 16 regions, 32byte granularity 16 channel DMA controller MEMORY 1.5M byte embedded program Flash 64K byte embedded data Flash (for EE Emulation) Up to 64MHz non-sequential access with 2WS ECC-enabled array with error detect/correct 96Kbyte SRAM (single cycle access, ECC-enabled) COMMUNICATIONS 6x enhanced FlexCAN 10 x LINFlex 6 x DSPI, 8-16 bits wide & chip selects 1 x I²C ANALOG Up to 52 ch 5V ADC (16x12-bit, 36x10-bit) resolution TIMED I/O 16-bit eMIOS module, 64ch. OTHER 32 Channel DMA Controller Debug: Nexus 2+ I/O: 5V I/O, high flexibility with selecting GPIO functionality Packages: 100LQFP, 144LQFP, 176LQFP, 208MAPBGA* (TBD) Boot Assist Module for production and bench programming JTAG VReg PowerPCTM e200z0 Core PIT 4ch 32b Power Mgt Nexus 2+ Oscillator DMA FMPLL Interrupt Controller CROSSBAR SWITCH Memory Protection Unit (MPU) I/O Bridge 1.5M Flash 96K SRAM Standby RAM Boot Assist Module (BAM) 64K Data Flash Crossbar Slaves Communications I/O System eMIOS 64ch, 16 bit 6 FlexCAN 10 LINFlex 6 DSPI 1 I2C Up to 52 ch ADC 16x12bit, 36x10 Bit

General Purpose Register (GPR)
Data Organization in Memory Big Endian - Most Significant Byte Big Endian – Least Significant Byte 31 32 63 0x0 A B C D E F G H 0x8 0x10 0x6 MSb 0 LSb 31 General Purpose Register (GPR) All MPC560xB instructions are either 16 or 32 bits wide. Power architecture is naturally Big Endian, but has switch for Little Endian Examples: Load word from address 0x0 loads the word “ABCD” Load half word from address 0x6 loads the half word “GH”

Start-Up Sequence POR monitors internal voltage and de-asserts itself
Default clock is the 16MHz IRC Boot configuration pins are sampled by the hardware - possiblity to go into e.g. serial boot mode Hardware checks reset configuration half word (RCHW) If hardware finds a valid RCHW (0x5A) it reads the 32-bit word at offset 0x04 = address where Start-Up code is located (reset boot vector). Device is put in static mode if no RCHW is found!

Flash and SRAM Overview
FLASH features: Up to 1.5MB Code Flash (MPC5607B) Up to 64k Data Flash on MPC560xB; same emulated EEPROM concept for most products of the MPC560xB family (sectorization; software compatibility; memory mapping) 64-bit programming granularity (can change value from 10 only) Read-while-write with Code and Data Flash or by RWW feature Erase granularity is Sector size 64-bit ECC with single-bit correction (and visibility), double bit detection for data integrity RAM features: User transparent ECC encoding and decoding for byte, half word, and word accesses 32-bit ECC with single-bit correction (and visibility), double bit detection for data integrity ECC is checked on reads, calculated on writes CAUTION: ECC requires SRAM must be initialized by executing 32-bit write operations (32-bit word aligned) prior any read accesses Done in initialization code before main

Why did I get Reset? Functional Reset Sources:
Destructive Reset Sources: Power On Reset Software Watchdog 2.7V Low-voltage detected 1.2 Low-voltage detected in Power Domain 1 1.2 Low-voltage detected in Power Domain 2 Status flag associated with a given ‘destructive’ reset event is set in the Destructive Event Status Register (RGM_DES) Functional Reset Sources: External Reset Code or Data Flash Fatal Error 4.5V low-voltage detected CMU clock freq higher/lower than reference FXOSC freq. lower than reference FMPLL failure Checkstop reset Software reset Core reset JTAG initiated reset Status flag associated with a given ‘functional’ reset event is set in the Functional Event Status Register (RGM_FES)

Debug, Software & Tools RAppID: Rapid Application Initialization and Documentation
RAppID PinWizard: Wizard workflow to allocate pins to peripherals Generates spreadsheet Inputs to RAppID Init Free utility RAppID Init: Generates initialization code for startup from CRT0 Generates interrupt handler code & framework Has ability to define section map and place code into any desired section

Debug, Software & Tools RAppID PinWizard Screenshot

System Integration Unit Lite (SIUL) Pad Configuration, Simple I/O
MPC560xB System Integration Unit Lite (SIUL) Pad Configuration, Simple I/O

Peripherals SIUL Introduction
Pad Control and IOMux configuration: Intended to configure the electrical parameters and I/O signal multiplexing of each pad; may simplify PCB design by multiple alternate input / output functions General Purpose I/O (GPIO) ports: Can write to GPIO data output pin or port Can read GPIO data input pin or port External interrupt management Allows the enabling and configuration (such as filtering window, edge and mask setting) of digital glitch filters on each external interrupt pin

Peripherals SIUL Pad Control and IOMux configuration overview
Pad Control is managed through Pad Configuration Registers (PCRs) IOMux configuration is managed through: PCR Registers (output functionalities) PSMI Registers (input functionalities)

SIUL Pad Control and IOMux config
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SMC APC PA OBE IBE ODE SRC WPE WPS W Reset SIUL Pad Control and IOMux config Pad Configuration Reg. (PCR) IP 1 IP 2 IP 3 IP 4 PCRn.PA IP a PSMI.PADSEL b) PCRn.OBE PCRn.IBE PAD n PCRn.SMC PCRn.SRC a) PCRn.APC ADC ch #… PCRn.WPE PCRn.WPS PAD m SoC Safe Mode PCRn.ODE Pad Select Multiplexed Inputs (PSMI) reg.

Peripherals SIUL Pad Control and IOMux configuration 2/4
Alternate functions are chosen by PCR.PA bitfields: PCR.PA = 00 -> AF0; PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11-> AF3. This is intended to select the output functions; For input functions, PCR.IBE bit must be written to ‘1’, regardless of the values selected in PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “--”.

Peripherals PSMI SIUL Pad Control and IOMux configuration 3/4
IP “n+1” PAD j PAD k PAD l PAD m PSMIn_n+3 Register

Peripherals SIUL Pad Control and IOMux configuration 4/4
Different pads can be chosen as possible inputs for a certain peripheral function.

Peripherals SIUL GPIO Functionality
PAD Control PCR Regs PSMI Regs GPIO functionality Data IOMux & PADs Pad Inputs Ext. Interrupt Mgmt Interrupt Controller Interrupt config Glitch filter

SIUL General Purpose I/O
GPIO pads can be managed two ways: On individual base (R/W access to a single GPIO); Access is done on a byte basis On port base (parallel access). Ports accesses can be: Data Read: 32-bit, 16-bit or 8-bit accesses Data Write: 32-bit, 16-bit or 8-bit (only if not masked access) Masked Access: This mechanism allows support for port accesses or for bit manipulation without the need to use read-modify-write operations Code example for writing to individual GPIO pin: SIU.PCR[68].B.PA = 0; /* Port E4 pin: Pad Assignment is GPIO */ SIU.PCR[68].B.OBE = 1; /* Port E4 pin: Output Buffer Enabled */ SIU.GPDO[68].R = 1; /* Port E4 pin: write 1 to Data Output */

MPC560xB Clocks

Platform Overview – Clocks
Clock Sources for Code Execution, System Clock (sysclk) 4-16 MHz External Crystal/Oscillator -> FXOSC Input to phase lock loop (FMPLL) to generate up to 64 MHz sysclk FMPLL has frequency modulation option to reduce EMC 16 MHz Internal RC Oscillator -> FIRC Default system clock after Reset Trimable Low Power Clock Sources 32 KHz External Crystal/Oscillator -> SXOSC Low power oscillator Dedicated for RTC/API 128 KHz Internal RC Oscillator -> SIRC Dedicated for RTC/API and watchdog

Platform overview – Clocks
Clock Monitor Unit (CMU) for PLL clock monitoring : detect if PLL leaves an upper or lower frequency boundary Crystal clock monitoring : monitors the external crystal oscillator clock which must be greater than the internal RC clock divided by a division factor given by RCDIV[1:0] of CMU_CSR register. Frequency meter : measure the frequency of one clock source versus a reference clock. CMU “event” (failure) will cause reset, SAFE mode request or interrupt request If fFXOSC_clk is less than fFIRC_clk divided by 2RCDIV bits of the CMU_CSR and the FXOSC_clk is ‘ON’ as signalled by the MC_ME then: • An event pending bit OLRI in CMU_ISR is set. • A failure event OLR is signalled to the MC_RGM which in turn can automatically switch to a safe fallback clock and generate an interrupt or reset. RCDIV may be set from 1 to 8 factor

Platform overview – Clocks MPC560xB CGM Clocking Structure
System Clock Selector (ME) Core Platform FXOSC 4-16MHz FXOSC_DIV div 1 to 32 SYSCLK FIRC 16MHz FIRC_DIV div 1 to 32 div 1 to 16 Peripheral Set 1 FMPLL div 1 to 16 Peripheral Set 2 FIRC RESET SAFE INT CMU FXOSC div 1 to 16 Peripheral Set 3 32KHz 128KHz SXOSC SIRC FIRC_DIV API / RTC SXOSC 32KHz div 1 to 32 SXOSC_DIV div 1 to 32 SIRC_DIV SIRC 128KHz SWT (Watchdog) FXOSC CLKOUT Selector FIRC CLOCK OUT FMPLL div 1/2/4/8

Platform overview – Clocks MPC560xB CGM System Clock
Provides the clock (divided or not) to the Core/Peripherals Selected by ME_XXX_MC register (XXX is desired mode) in the Mode Entry (ME) module System Clock Selector (ME) Core Platform Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 Enable & div 1 to 16 SYSCLK FXOSC FIRC FMPLL FIRC_DIV FXOSC_DIV

Platform overview – Clocks MPC560xB CGM System Clock Divider Configuration Register
Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 All LINFlex modules All FlexCAN modules All eMIOS modules I2C module All DSPI modules CTUL ADC System clock global switch to peripheral set. Local switch for each peripheral at ME_PCTL. DEx: Peripheral Set x Divider Enable (Default value 1 = ON) DIVx: Peripheral Set x Divider x Division Value (1..15)

Platform overview – Clocks MPC560xB CGM Output Clock Description
Clock output on the GPIO[0] (PA[0]) pin Watch out: max pad slew rate! FXOSC CLKOUT Selector FIRC div 1/2/4/8 CLOCK OUT (GPIO[0]) FMPLL SELDIV: division by 1, 2, 4, 8 SELCTL: clock source (XOSC, FIRC, PLL) selection

The PLL output clock frequency derives from the relation:
CGM FMPLL Normal mode The PLL output clock frequency derives from the relation: (FXOSC x NDIV) (IDF x ODF) FMPLL = Input divider 1..15 Output divider 2/4/8/16 4 4MHz 128MHz FMPLL 16MHz 2 64MHz 32 Mold Array Process-Ball Grid Array Loop divider 32..96 Example: FXOSC = 16MHz FMPLL = 64MHz  NDIV = 4 * IDF * ODF  NDIV = 32 , IDF = 4 , ODF = 2

CMU Ref.: Clock Monitor Unit Tasks
The first task of the CMU is to permanently supervise the integrity of the various product’s clock sources, e.g. FXOSC or FMPLL, if either FXOSC clock frequency lower than FIRC / 2n PLL clock frequency upper or lower frequency boundaries defined in CMU registers If an integrity problem occurs, the Mode Entry module is notified in order to switch to SAFE mode with FIRC as clock source. The second task is frequency measurement. It allows to measure the deviation of a clock (FIRC, SIRC or SXOSC ) by measuring its frequency versus FXOSC as reference clock. Can be used to improve IRC calibration Can be used for Real Time Counter precision

CMU Ref.: Crystal Clock Monitor
Crystal clock monitor is active only when ME provides the info that FXOSC is valid If FXOSC < FIRC / 2RCDIV (CMU_CSR[RCDIV] bits), then an event pending bit CMU_ISR[OLRI] is set. a failure event is signaled to the RGM which in turn can generate a RESET, transition to SAFE mode, or generate an interrupt request FXOSC supervisor FFXOSC < FFIRC / 2RCDIV FXOSC FIRC CMU_ISR register RGM, ME FXOSC stable/unstable FXOSC Failure

CMU Ref.: Crystal Clock Monitor Reset Default Values
CAUTION: Before enabling crystal clock input in a mode configuration, verify the proper compare frequency divider. MPC560xB, MPC560xS: reset default RCDIV = 3, so FreqFIRC / 2CMU_CSR[RCDIV] = 16 MHz / 8 = 2 MHz MPC560xP: reset default RCDIV = 0, so FreqFIRC / 2CMU_CSR[RCDIV] = 16 MHz / 1 = 16 MHz

CMU Ref.: Crystal Clock Monitor Event Behavior
Oscillator Less than Reference event occurs when the FXOSC appears too slow and sets: CMU_ISR[OLRI] No interrupt or other automatic action can be generated – just sets the bit RGM_FES[F_CMU_OLR] Action taken is per table below: Functional Event Reset Disable: FXOSC freq. lower than reference Functional Event Alternate Request: Alternate Request for FXOSC freq. lower than reference Action RGM_FERD [D_CMU_OLR] RGM_FEAR [AR_CMU_OLR] 0 (reset default) - Reset sequence 1 SAFE mode request Interrupt request – INTC #56

CMU Ref.: FMPLL Monitor – Frequency Range
FMPLL monitoring is enabled at CMU_CSR(CME) Monitoring is active only when ME provides the info that FMPLL is valid. Depending on the following conditions If FFMPLL is lower than HLREF[11:0] bits in CMU_LFREFR If FFMPLL is higher than HFREF[11:0] bits in CMU_HFREFR

CMU Ref.: FMPLL Monitor – Failure Behaviour
Then for each matching: a dedicated event pending bit in CMU_ISR is set. a failure event is output to the RGM & ME which can generate a transition to SAFE mode, an interrupt or a reset sequence. ME, RGM FMPLL stable/unstable FMPLL Failure CMU_ISR register FMPLL CMU_HFREF register Fpll < LFREF threshold CMU_LFREF register FIRC Fpll > LHREF threshold

RUN Modes Introduction
MPC560xB RUN Modes Introduction

Use Case: Conserving Power While Software Runs (1 of 2)
Software runs one of the three following tasks: Analog Monitor Uses ADC to look for particular voltages on inputs Only requires 16 MHz FIRC, which is also sysclk If analog input measurements meet a criteria, software transitions to the communication task Communication Uses FlexCAN_0, FlexCAN_1 to transmit analog data and receive response Only requires FXOSC, which is also sysclk If response is positive, software transitions to the whole chip task Whole Chip Requires all peripherals active Sysclk = 64MHz FMPLL, which also requires FXOSC

Use Case: Conserving Power While Software Runs (2 of 2)
Run Mode sysclk Clock Sources Req’d Peripherals Requiring Enabled Clock FIRC XOSC FMPLL  Mode Configuration   Peripheral Configuration  RUN0: AnalogMon X ADC, SIU RUN1: Comm FlexCAN_0, FlexCAN_1, SIU RUN2: WholeChip All Peripherals Peripheral Control Reg. # Modes with Enabled Clock RUN Mode Peripheral Configuration RUN0 RUN1 RUN2 RUN3 ADC 32 X Run PC0 FlexCAN_0, 1 16, 17 Run PC1 SIU 68 Run PC2 All others Other #’s Run PC3

The Mode Entry Module (MC_ME) provides SYSTEM modes and USER modes :
Mode Overview The Mode Entry Module (MC_ME) provides SYSTEM modes and USER modes : SYSTEM: RESET, DRUN (Default RUN), SAFE and TEST USER: RUN(0..3), HALT, STOP and STANDBY For each mode the following parameters are configured/controlled System clock sources (ON/OFF) System clock source selection Flash power mode (ON, low power, power down) Pad output driver state (For low power modes - can disable Pad Output drivers, enabling high impedance mode) Peripherals’ clock (gated/clocked) TEST/SAFE – high impedance, inputs unchanged STOP – high impedance, outputs unchanged STANDBY – high impedance, except WKUPs

HW triggered transition SW triggered transition
Device Modes - Diagram USER MODES SYSTEM MODES LOW POWER MODES RUN 0 Recoverable HW failure SW request SAFE HALT RUN 1 RESET DRUN STOP RUN 3 TEST Non recoverable HW failure STANDBY HW triggered transition SW triggered transition

ME_xxx_MC - Mode Configuration Registers
Each mode has a Mode Configuration register. Example: ME_DRUN_MC Key RUN mode configurations are circled: CFLAON DFLAON MVR ON reserved PDO OSC SYSCLK IRC PLL 1 4 7 8 9 15 3 2 6 5 12 13 14 11 10 17 20 23 24 25 31 16 19 18 22 21 28 29 30 27 26 PDO: Disable pad outputs (put in hi Z) MVRON: control VREG on/off CFLAON/DFLAON: control code / data flash module Normal Low Power Power Down PLLON: control PLL on/off OSCON: control XOSC on/off IRCON: control IRC16M on/off SYSCLK: select system clock

Mode Configurations Example
It is useful to keep a table of mode configurations used. Example below uses two USER modes. (Per AN2865 rev 4)

Peripheral Clock Gating Control
Each peripheral can be associated with a particular clock gating policy The policy is determined by two groups of peripheral configuration registers: ME_RUN_PC0:7 for RUN modes ME_LP_PC0:7 for Low Power modes Clocks to peripherals are gated off unless enabled for that mode Example (per AN2865 rev 4):

MC_ME Peripheral Configuration Registers RUN Modes
Defines a selection of 8 possible RUN mode configurations for a peripheral

Device Start-up: MC_ME Peripheral Control Registers
For each peripheral, there is a ME_PCTLx register to control clock gating to that peripheral: - selects one of the 8 Run peripheral set configurations - selects one of the 8 Low Power peripheral set configurations - enables/disables freezing the clock during debug Peripheral 143 Peripheral 3 Peripheral 2 Peripheral 1

Mode Entry: SW and HW Transitions
Software handled transition A transition is requested writing a key protected sequence in ME_MCTL Mode Entry configures the modules according to the ME_xxx_MC register of the target mode Once all modules are ready the new mode is entered Transition completion signalling: status bit/interrupt Note: Modification of a ME_xxx_MC register (even the current one) is taken into account on next mode “xxx” entry Hardware triggered transition Exit from low power mode SAFE transition caused by HW failure RESET transition caused by HW failure

RUN mode configurations allow
Review of Key Points RUN mode configurations allow Enabling/disabling system clock sources Selecting appropriate system clock Gating clocks to peripherals Peripheral clocks can be divided as needed on a set basis Example PLL: Initializing System Clock

Exercise: Initialize PLL & RUN Mode, Write GPIO Output
Open existing CodeWarrior Project, “PLL-sysclk” Navigate to the PLL-sysclk project for MPC560xB. Example path: C: \ Program Files \ Freescale \ CW for MPC55xx and MPC56xx \ (CodeWarrior_Examples) \ 560xB-CW \ PLL-sysclk Double click on the project file “PLL-sysclk.mcp” to open it in CodeWarrior Compile and link RAM project Either a) click: Project – Make – or-- b) click on the make icon Download to target Connect EVB to PC with USB cable Either click: Project – Debug, or, click on the Debug icon Click the “Connect” button Type “gotil main” in the Status Window Initialize registers to turn on LED1 on target board Click the “REG” button at the top Click “SIUL System Integration Unit Lite” Set bit fields for a GPIO output (PCR68: PA=1, OBE=1; GPDO68: PDO=1) Exit register windows then open again to validate the register was altered Are registers still shown as modified? Execute thru initModesAndClock &re-try.

Timed I/O (Watchdog, PIT & eMIOS)
MPC560xB Timed I/O (Watchdog, PIT & eMIOS)

Watchdog Timer – Regular Mode Servicing
To prevent the watchdog from interrupting or resetting, the following sequence must be performed before a timeout period: Write 0xA602 to the SWT_SR Write 0xB480 to the SWT_SR Note: other instructions, such as an ISR, can occur between above writes

Programmable Interrupt Timer (PIT) Features
Clocked by system clock 32-bit counter Independent timeout periods for each timer Timer can generate interrupt/DMA request, ADC conversion PIT # Interrupt Request DMA Request Peripheral Trigger YES NO 1 2 10-bit ADC 3 CTU ch23 (can trigger ADC) 4 5 6 12-bit ADC 7 CTU ch55 (can trigger ADC)

Crossbar Switch (XBAR) Memory Protection Unit (MPU) 8 regions
eMIOS260 Introduction Crossbar Switch (XBAR) INTC Memory Protection Unit (MPU) 8 regions Integer Execution Unit Multiply Instruction Unit VLE General Purpose Registers (32 x 32-bit) Branch Unit Load/Store Unit e200z0h Core (C)JTAG Debug RAM Controller SRAM (ECC) FLASH Code Flash Data FLASH Peripheral Bridge LINFlex 3 - 8 DSPI 2 - 4 FlexCAN 1 - 6 ADC10 16 – 57 ch eMIOS-lite 24 – 56 ch API/RTC PIT 6 ch STM 4 ch I2C 1 SIU SWT BCTU VREG OSC 32K IRC 16M PLL IRC 128K OSC 4-16M Provides various modes to generate or measure timed event signals. 24 to 56 Channels One new channel mode featuring lighting applications, OPWMT All other channel modes are subset of the unified channel structure on previous eMIOS. Consistent user interface with previous eMIOS implementation.

eMIOS Channel Modes Type Abbr. Channel Mode Counter MCB
Modulus Counter (up or up/down) Input SAIC Single Action Input Capture IPWM Input Pulse Width Measurement IPM Input Period Measurement Output SAOC Single Action Output Compare DAOC Double Action Output Compare OPWMB Output Pulse Width Modulation OPWMT Output Pulse Width Modulation with Trigger OPWFMB Output Pulse Width & Frequency Modulation OPWMCB Center aligned Output Pulse Width Modulation with dead time

Example: MPC5604B eMIOS channel configuration

MPC5605/6/7B Block Structure
2 EMIOS Blocks – EMIOS_A and EMIOS_B Each Block contains 32 Unified Channels Common System Clock Devider Separate Global Prescaler System Clock (/1,2,4,8,16) Default /1 EMIOS_B EMIOS_A Channel 0 Prescaler (/1, 2, 3, 4) Channel 0 Prescaler (/1, 2, 3, 4) Global Prescaler (/1, 2, 3, … 256) Global Prescaler (/1, 2, 3, … 256) Channel 31 Prescaler (/1, 2, 3, 4) Channel 31 Prescaler (/1, 2, 3, 4)

eMIOS260 Unified Channel Features
Selectable time base for each counter bus Programmable Clock Prescaler Double buffered data registers and comparators State Machine (with mode control) Programmable as input or output: Input Edge Detect as rising, falling or toggle. Programmable digital input filter

eMIOS260 Double Buffered A and B Registers
A and B data registers are double buffered to provide a mechanism for safe update of the A and B register values This also enables very small pulse / period generation or measurement since updates can happen in current period The channel A user registers are an address mapped link to either the A1 or A2 register (determined automatically by the mode of the unified channel). For output modes, data is typically written to the A2 register For input capture modes, data is latched into either A1 or A2 depending on mode. All of this is transparent to the user Comparator A Note – Same applies to B set registers as well! Register A1 UCAn Register (User Accessible) Register A2

Peripherals EMIOS counter buses
UC[27] Counter Bus A The MPC560xB family has 5 shared counter busses allowing common counter bus timing across multiple channels Counter Bus A is shared with all channels and driven from channel 23 Counter bus B is shared with channels 0 to 7 and driven from channel 0 Counter bus C is shared with channels 8 to 15 and driven from channel 8 Counter bus D is shared with channels 16 to 23 and driven from channel 16 Counter bus E is shared with channels 24 to 27 and driven from channel 24 Counter Bus E UC[24] UC[23] Counter Bus D UC[16] UC[15] Counter Bus C UC[8] UC[7] Counter Bus B UC[0]

Peripherals EMIOS - Single Action Input Capture
Returns the value of the counter bus on an edge match of an input signal . Can use Internal or Modulus counter Can match on Rising, Falling or Toggle determined by state of EDPOL, EDSEL Edge detect Edge detect Edge detect input signal selected counter bus FLAG pin / register A2 (captured) value $xxxxxx $000500 $001000 $001100 $001250 $001525 $0016A0 $001000 $001250 $0016A0 $001000 $001250 $0016A0 Notes: When edge is detected, flag is set and counter bus value is captured in register A2. User reads this value from UCA[n] register. UCB[n] = Cleared and cannot be written Example with detection on rising edge

Peripherals EMIOS - Modulus Counter Buffer Mode – UP Counter
Generates a time base which can be shared with other channels through the internal counter buses Can use Internal or External (input channel pin) counter FLAG pin / register A1 value A2 value Internal Counter (UCCNTn) 0x000001 0x001000 0x000800 $001000 $001000 $001000 $000800 $000800 $001000 $000800 $000800 A1 match write into A2 A1 match update of A1 A1 match Examples with output High and Toggle Notes: On a comparator A match, FLAG is set and the internal counter is set to value $1. Allowing smooth transitions, a change of the A2 register makes the A1 register be updated when the internal counter reaches the value $1. Caution – If when entering MCB mode the internal counter value is upper than register UCA[n] value, then it will wrap at the maximum counter value ($FFFFFF) before matching A1.

Peripherals EMIOS - OPWMFMB
Generates a simple output PWM signal Requires INTERNAL Counter EDPOL allows selection between active HIGH or active LOW duty cycle. B1 value A1 value Selected counter bus A2 value output flip-flop EDPOL=1 EDPOL=0 0x001000 0x000800 0x000200 $001000 $001000 $001000 $001000 $000200 $000200 $000200 $000800 $000800 $000200 $000800 $000800 A1 match B1 match write into A2 A1 match B1 match update of A1 A1 match B1 match Notes: Duty Cycle = UCA[n] (A1) + 1, Period = UCB[n] (B1) + 1 On Comparator A1 match, Output pin is set to value of EDPOL On Comparator B1 match, Output pin is set to complement of EDPOL and Internal counter is reset The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle. FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit.

Peripherals EMIOS - OPWMB
Generates a simple output PWM signal Can use Internal or Modulus counter EDPOL allows selection between active HIGH or active LOW duty cycle. Selected counter bus $000800 $000200 B1 value A1 value A2 value output flip-flop EDPOL=1 B2 value 0x001000 0x000800 0x000600 0x000400 0x000200 $000800 $000800 $000600 $000600 $000600 $000600 $000200 $000200 $000400 $000400 $000400 $000400 A1 match B1 match write into A2 & B2 A1 match B1 match update of A1 & B1 Notes: Write UCA[n] (A1) with Leading Edge. Write UCB[n] (B1) with trailing edge On Comparator A1 match, Output pin is set to value of EDPOL On Comparator B1 match, Output pin is set to complement of EDPOL The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle. FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit.

Peripherals EMIOS - OPWMT
Generates a PWM signal with a fixed offset and a trigger signal Intended to be used with other channels in the same mode with shared common time base This mode is particularly useful in the generation of lighting PWM control signals. output flip-flop EDPOL=1 FLAG pin / register Selected counter bus 0x001000 0x000800 0x000600 0x000400 0x000200 B1 value $000800 $000800 $000800 $000600 $000600 B2 value $000800 $000600 $000600 A1 value $000200 $000200 $000200 $000200 A2 value $000400 $000400 $000400 $000400 A1 match A2 match B1 match A1 match A2 match write into B2 B1 match Update of B2 A1 match A2 match B1 match Notes: A1[n] defines the Leading Edge, B1[n] the trailing edge, A2[n] the generation of a FLAG event On Comparator A1 match, Output pin is set to value of EDPOL On comparator A2 match, FLAG is set (and can allow to synchronize with other events, ie. AD conversion) On Comparator B1 match, Output pin is set to complement of EDPOL The transfers from register B2[n] to B1[n] is performed at every match of register A1

Peripherals EMIOS - Programmable Input Filter
Filter Consists of a 5 bit programmable up-counter, clocked by either the channel or peripheral set clock (defined by FCK) Input signal is synchronised to system clock. When the synchroniser output changes state, the counter starts counting up If the synchroniser state remains stable for the desired number of selected clocks, the counter overflows on next high clock edge, counter resets and filter output changes FCK IF3 IF2 IF1 IF0 Prescaled Channel CLK CLK 5-Bit Up Counter Filter Out Peripheral Set CLK Synchroniser PIN Filter can be set to trigger after 2,4,8 or 16 clocks (or bypassed) Notes – If Input signal changed state on 3rd clock of filter cycle (ie just before counter overflow in diagram above), counter would STILL overflow and output would toggle. In reality, there is a 3 clock cycle delay between counter overflow and filter out occuring. Clock 1 Start 1 Start 1 Start 2 3 4 Start 1 2 Start 1 1 Start Input Sig Overflow IF[0:3] = 0010 5-bit counter Filter Out

eMIOS channels can be configured for desired timing function
Review of Key Points eMIOS channels can be configured for desired timing function Input functions: SAIC, IPM, IPWM, GPIO Output functions: DAOC, OPWM, OPWMT, OPWMC, OPWFM, GPIO Modulus counter Global, local or individual channel time bases Input functions can share common time base Output functions can be synchronized Example eMIOS OPWM, Modulus Counter

MPC560xB Interrupts

MPC5604B Interrupt Structure
Interrupt Requests from Interrupt Controller (INTC) Interrupt Requests from Core Exceptions (e200z0) 8 Software 3 MCM 2 Wdog & clock 4 STM Critical Input 2 RTI/API INTC in Software Vector Mode Machine Check 5 SIU & WPU Data Storage CPU Interrupt 5 Magic Carpet Instruction Storage 6 PIT External Input 3 ADC Alignment 54 CAN Program 1 IIC System Call 28 eMIOS Debug 15 DSPI CPU Core 12 LIN INTC interrupts are assigned one of 16 priority levels, enabling premption

Hardware context switch:
Interrupt Behavior Interrupt is recognized Hardware context switch: Stores address of next instruction or instruction causing interrupt Stored into special purpose reg. Save & Restore Reg 0 (SRR0) Stores Machine State (MSR bits 16:31): Stored into special purpose reg. Save & Restore Reg 1 (SRR1) Alters Machine State: All bits are cleared in MSR except ME Alters Instruction Pointer: points to unique interrupt vector Software Interrupt handler (at interrupt vector) Execute your handler code, including save/restore registers Last instruction, rfi*, (return from interrupt): Restores MSR bits 16:31 from SRR1 Restores instruction pointer from SRR0 * “Critical” and “debug” interrupts use rcfi and rdfi instruction instead of rfi.

External input Exception (EE)
e200z0 Core Interrupts External input Exception (EE) enables/disables all interrupts from the interrupt controller. Each exception type can normally be individually enabled or disabled in the Machine State Register (MSR) Core Interrupt Type IVOR # IVPR Offset Critical Input IVOR 0 0x000 Machine Check IVOR 1 0x010 Data Storage IVOR 2 0x020 Instruction Storage IVOR 3 0x030 External Input IVOR 4 0x040 Alignment IVOR 5 0x050 Program IVOR 6 0x060 System Call IVOR 8 0x080 Debug IVOR 15 0x0E0

INTC: MPC560x Software & Hardware Vector Modes
4/15/2017 INTC: MPC560x Software & Hardware Vector Modes Address Instructions IVPR0: x40 prolog (including using IACKR to get vector then bl ISR_n) epilog Address ISR Vector Table2 Core’s VTBA ISR_0 address ISR_1 address … ISR_n address ISR_286 address INTC’s IRQ n taken ISR_0 ISR ISR_n ISR_286 Core’s IACKR Software Vector Mode handler_0 prolog ISR epilog handler_n handler_291 . Hardware Vector Mode Handler Branch Table Address Instructions1 IVPR0:19 + 0x800 b handler_0 IVPR0:19 + 0x804 b handler_1 IVPR0:19 + 0x808 b handler_2 … IVPR0: x n(0x4) b handler_n IVPR0:19 + 0x0C8C b handler_286 Notes: “b handler_n” instruction is technically part of the handlers. ISR Vector Table alignment in software vector mode assumes INTC_MCR[VTES]=0. . INTC’s IRQ n taken HP presentation template tutorial - Rev. 1

Interrupt Vector Core Interrupts & INTC Software Vector Mode Interrupts
The interrupt vector address is composed of two components: Vector base address used as a prefix (special purpose register IVPR bits 0:19) A fixed offset base on the IVOR # Each interrupt vector address would contain your branch instruction to that handler. Example: Core interrupt IVOR 4 taken: Base Address IVPR IVOR0 IVOR1 IVOR2 IVOR15 IVOR3 IVOR4 Execute branch to IVOR4 handler Jump to address in Prefix Register (IVPR) + offset of 0x40 for IVOR4

Interrupt controller INTC Preemption
Interrupt sources are assigned 1 of 16 priority levels 15 is highest priority, 0 is lowest Each interrupt source’s priority is specified in its Priority Select Register (8 bits wide), INTC_PSRx The Interrupt Controller records the current interrupt’s priority. - The current priority is in the Current Priority Register, INTC_CPR - Only interrupts with a priority higher than current priority can be recognized, allowing preemption. Preempted priorities are automatically pushed/popped to/from a LIFO in the interrupt controller.

INTC Software Vector Mode
Review of Key Points INTC Software Vector Mode INTC Interrupt vector is fetched by software Memory efficient due to common prologue, epilogue INTC Hardware Vector Mode INTC Interrupt vector is automatically fetched by hardware Saves some time Example INTC SW mode with VLE, or INTC HW mode with VLE

MPC560xB ADC, CTU

(19 channels can be shared) Add’l channels w. mux. Up to 28 Up to 44
ADC: Overview Feature MPC5604B MPC5605/6/7B Resolution 10 bit ADC 10 bit ADC & 12 bit ADC Number of channels 28 or 36 channels Up to 48 channels: 19 12-bit, 29 10-bit (19 channels can be shared) Add’l channels w. mux. Up to 28 Up to 44 Accuracy (TUE) 2 LSB internal 3 LSB external (mux.) Minimum conversion time 1 usec Input range 0 – 5V Output Dedicated result registers

ADC: MPC5607B Mapping: Signals, ADC, CTU
Signal Name (per Table 2-3) * Not on MPC5604B/C ADC Channel # (per Fig 23-1) CTU EVTCFTRx [CHANNEL_VALUE] ADC0 ADC1* ANP 0:15* 0:15 - ANS 0:7 32:39 ANS 8:27* 40:59 ANX 0, MA 0:7 64:71 ANX 1, MA 0:7 72:79 40:47 ANX 2, MA 0:7 80:87 48:55 ANX 3, MA 0:7 88:95 56:63

ADC: MPC560xB Trigger Options
Selected Channels Trigger Initiation Trigger Enables Normal Scan or One shot modes Multiple, as selected in NCMR (Normal Conversion Mask Register) Software sets NSTART bit None Injected One shot mode only Multiple, as selected in JCMR (inJected Conversion Mask Register) Software sets JSTART bit or PIT2 expires Software: none PIT2: PIT2 configured and MCR[JTRGEN] Cross Trigger Unit (CTU) Single, as selected in CTU_EVTCFGRx [CHANNEL_VALUE] PIT3, PIT7 or eMIOS channels (up to 46) CTU_EVTCFGRx MCR[CTUEN & ADC_SEL] EMIOS_CHx_CCR [DMA, FEN]

SUCCESSIVE APPROXIMATION A/D CONVERTER
ADC: Block Diagram AIN0 AIN1 ADC data registers SAMPLE & HOLD 10 bit Converter D95 D94 . D1 D0 ANALOG MUX End of conversion End of injection Threshold Violation Interrupts SUCCESSIVE APPROXIMATION A/D CONVERTER AINx ANALOG MUX EMIOS Timer channels Cross triggering Unit ADC_PRE-EMPTS Max internal frequency to be verified! 2 prescalers: 1 for sampling, 1 for conversion result Trigger event for injected conversion The CTU will automatically signal the channel to be converted by hardware ADC_CONTROL Analog watchdog

Normal conversion mode
ADC: Conversion Modes Normal conversion mode one–shot mode or scan mode possible

ADC: Programmable Analog Watchdog
4 to 6 Analog Watchdogs can monitor any ADC channel Number depends on device implementation Programmable UPPER and LOWER threshold Dedicated ADC (WD) Interrupt on UPPER and/or LOWER threshold violation Can be used in a lighting application to trim SMARTMOS devices to prolong LED life Use EMIOS (OPWMT mode) -> CTU -> ADC to continually monitor LED voltage 0% CPU loading Only use CPU in event of ADC watchdog interrupt WDOg detects very low and high current i.e light bulb. PWM signal can be adjusted by software to reduce current drive to prolong bulb life or can detect 0 current to indicate bulb is burned out.

ADC Channel Masks Individual channel mask bits enable: Normal conversion Injected conversion

ADC – Channel Data Registers
Each channel has a data register containing: VALID indication of new value written (cleared when read) OVERWrite data indication that previous conversion data is overwritten by a new conversion RESULT indication of conversion mode: normal, injected, CTU CDATA with channel’s converted data value

Each ADC converter has two interrupt vectors to the INTC:
ADC Interrupts Each ADC converter has two interrupt vectors to the INTC: ADC_EOC: ADC End of conversion End of (normal) chain conversion End of (normal) channel conversion (channels selected separately) End of injected chain conversion End of injected channel conversion End of CTU conversion ADC_WD: ADC watchdog Watchdog0:3 or 5 high thresholds exceeded Watchdog0:3 or 5 low thresholds exceeded

CTU: Purpose The Cross Triggering Unit Lite on the MPC560xB family is a link between timers (eMIOS or PIT) and the ADC The CTU “Lite” (as on MPC560xB) automatically transforms timer events into ADC conversions without main CPU intervention The real-time behavior (synchronization) between timer events and ADC conversions is guaranteed

CTU: MPC54605/6/7B Trigger Events
eMIOS eMIOS A0 Ch0 Trig eMIOS A22 Ch22 Trig 10-bit ADC eMIOS A24 Ch24 Trig ADC Control eMIOS A31 Ch31 Trig ADC Trigger eMIOS B0 Ch32 Trig ADC Done eMIOS B22 Ch54 Trig CTU Injection trigger eMIOS B24 Ch56 Trig ADC Control 12-bit ADC eMIOS B31 Ch63 Trig PIT Ch23 Trig ADC Trigger PIT Ch55 Trig ADC Done PIT PIT2 Injection trigger PIT6

PWM & Diagnosis Timing Calculations: Definitions:
Ch 0 Ch 1 Ch n-1 Ch n 200Hz channels (n+1) tchd tirsd tdw ADC Calculations: 200Hz ms Period MDDC = 8% of 5ms = 400us tdwmin = MDDC – tirsd tdwmin = 400us -300us = 100us Definitions: PWM 200Hz (0.35% resolution, xybit) MDDC: 8% (Min Diag Duty Cycle: For Duty cycles <8% no diagnosis is required) tchd: 1ms (Channel Delay to control inrush current as well as EMC on ECU level) tirsd: 300us (Inrush Delay to ensure ADC measurement takes place once current is stable) tdwmin: 100us (Diagnosis Window = Min. Diag. Duty Cycle – Inrush Delay)

eMIOS OPWMT Mode: Allows
Period B1 C1 A1 Output Pin Match A1 Match A2 Match B1 Period: the period of the PWM is defined by a Modulus Counter channel. A1 Value: define the leading edge (or shift) of the PWM channel. Buffering is not needed as the value of the shift must not changed on the fly. B1 Value: define the trailing edge (or duty cycle) of the PWM channel B2 Value: buffered value of trailing edge B1 update: transfer from B2 to B1 takes place at A1 match EDPOL: define the output polarity A2 Value: define the sampling point for the analog diagnostic. It can be configured anywhere within the PWM period.

MPC560xB eDMA

enhanced Direct Memory Access (eDMA)
DMA is often an alternative to CPU interrupt Peripheral flag causes DMA request (instead of interrupt request) to transfer data Data is transferred from a “source” to a “destination” DMA channels have a “transfer control descriptor” (TCD) to describe this transfer Multiple different transfers can take place with a single DMA request using “channel linking” or “scatter gather” Allows combining multiple peripherals to a new “super” peripheral

eDMA: Selecting a DMA source
Disabled DMA Channel Mux Source # 2 Source # 3 . DMA Channel #0 Peripherals DMA Channel #1 . Source # 21 Trigger # 1 DMA Channel # 15 . Always Enabled Trigger # 4 Software selects which DMA sources connect to the 16 DMA channels DMA request for channels can be initiated by: A peripheral (example: ADC conversion result ready to be put into queue) Software (example: set a bit to initiate a block move) Periodic Interval Timer (example: enable periodic transmit of latest pending SPI data) Periodic Interval Timer available to 4 of the 16 channels (DMA channel 0 to 3)

eDMA Mux: Channel Mux Source Options
DMA Mux Source Input # # sources DMA Source 1 Channel Disabled 1 – 12 12 6x DSPIs : transmit, receive 13 – 24 6x eMIOS_A / 6x eMIOS_B channels 25 ADC_0 10-bit converion complete 26 ADC_1 12-bit conversion complete 27-28 2 IIC_A receive, transmit 4 Always Enabled - with PIT to generate periodic DMA - w/o PIT for continuous DMA transfer

eDMA Mux: Channel Configuration
Channel Configuration Registers [0:15] By routing sources to channels 0-7 you can create an automatic mechanism for transferring data at a certain period. Triggered mode has 2 obvious uses: • Periodically polling external devices on a particular bus. As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above. After setup, the SPI requests DMA transfers (presumably from memory) as long as its transmit buffer is empty. By using a trigger on this channel, the SPI transfers can be automatically performed every 5 µs (as an example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. Using the GPIO ports to drive or sample waveforms. By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on-chip memory. TRIG (PIT generated DMA request) is only available for channels 0:7 (MPC5606B) PIT timers 1:8 provide the TRIG for DMA channels 0:7

eDMA: DMA channel triggering
Periodic Triggering “throttles” DMA by limiting transfers Peripheral Request gates with Trigger to cause DMA Request “Always enabled” DMA sources: all Triggers generate DMA request

eDMA: Transfer Control Descriptor (TCD) Introduction
One Transfer Control Descriptor (TCD) for each channel: Source, Destination addresses Separate Size for each read and write access Number of transfers per DMA request Total number of DMA requests serviced before stop or restart. Signed restart address adjustment Last Source Address Adjustment and Last Destination Address Adjustment Scatter/Gather support Source Address (saddr) Signed Source Address Offset (soff) Transfer Attributes (smod, ssize, dmod, dsize) Inner “Minor” Byte Count (nbytes) Destination Address (daddr) Signed Destination Address Offset (doff) Current “Major” Iteration Count (citer) Last Source Address Adjustment (slast) Last Destination Address Adjustment (dlast_sga) “Major” Iteration Counter (biter) Channel Control Status (bwc, linkch, done, active, e_link, e_sg, dreq, int_half, int_maj, start)

Current “Major” Loop Iteration Count (citer)
eDMA: TCD Loops Example Memory Array Current “Major” Loop Iteration Count (citer) DMA Request . Minor Loop 3 2 1 DMA Request . Minor Loop Major Loop DMA Request . Minor Loop Each DMA request initiates one minor loop transfer (iteration) without CPU intervention DMA arbitration can occur after each minor loop. One level of minor loop DMA preemption is allowed The number of minor loops in a major loop = beginning iteration count (biter).

. addr: size of one data transfer
eDMA: TCD Terms addr: starting address size of one data transfer Minor Loop . offset: number of bytes added to current address after each transfer (often the same value as size) nbytes in minor loop (often the same value as size) Each DMA source and destination has their own: addr size offset last Peripheral queues typically have size and offset equal to nbytes. . Minor Loop last: number of bytes added to current address after major loop (typically used to loop back)

Upper address bits retain their original value. Transfer # Address 1
eDMA: Modulo Feature Provides the ability to easily implement a circular data queue Size of queue is a power of 2 mod, a 5-bit bit field, specifies which lower address bits are allowed to increment from their original value after the address + offset calculation all upper address bits remain the same as in the original value. If mod = 0 disables modulo feature Example: source address = 0x ; offset is 4 bytes so mod=4, allowing for a 24 byte (16-byte) size queue Upper address bits retain their original value. Transfer # Address 1 0x 2 0x 3 0x 4 0x C 5 6 Another example, the mod field would be programmed with a value of 5 if the lower 5 bits are intended to be incremented, allowing for a 32-byte queue. Circular buffer - address wraps to original value Transfers Queue Data to multiple TPU Channels PRM0 PRM1 PRM2 PRM3 PRM4 PRM5 PRM6 PRM7 TPUC 1 TPUC 2 TPUC n 0…………31 PRM0 PRM1 PRM2 PRM0 PRM1 PRM2 PRM3 PRM4 PRM5 PRM6 PRM7 PRM3 PRM4 PRM5 PRM6 PRM7 O MOD = 5 Allowing Module 32. PRM0 PRM1 PRM2 PRM3 PRM4 PRM5 PRM6 PRM7 Module mode may be used when attempting To configure multiple TPU Channels for the same Functions in which they utilize the same Parameters. If we were to monitor the LSB 5 bits of the address in this operation, we will see Addr as 0, 4, 8, C, 10, 14, 18, 1C, 0, 4, 8, C, 10, 14, 18, 1C, 0,,,,,,etc.

eDMA: Scatter-Gather Feature
Allows a DMA channel to use multiple TCDs Enables a DMA channel to scatter the DMA data to multiple destinations or gather it from multiple sources Example use: linked list of LIN messages Example: TCD A (in flash or SRAM) TCD B (in flash or SRAM) sga (Scatter Gather Address) sga Sequence: Initialization: Load TCD A from flash to DMA channel x’s TCD 1st DMA request or START=1: Executes TCD A; TCD B loads automatically 2nd DMA request or START=1: Executes TCD B; TCD A loads automatically Option: TCD B could automatically execute with the 1st DMA request if the TCD’s start bit is set.

Desired Link Behavior TCD Control Field Name
eDMA: Channel Linking A DMA channel can “link” to another DMA channel, i.e, set the start bit of a 2nd TCD At the end of every minor loop (except the last one) And/or, at the end of the major loop Also enables linked lists Desired Link Behavior TCD Control Field Name Description Link at end of Minor Loop citer.e_link Enable channel-to-channel linking on minor loop completion (current iteration) citer.linkch Link channel number when linking at end of minor loop (current iteration) Link at end of Major Loop major.e_link Enable channel-to-channel linking on major loop completion major.linkch Link channel number when linking at end of major loop

eDMA: Other Control & Status Fields (1 of 2)
TCD Control Field Name Description start Control bit to explicitly start channel when using a software initiated DMA service. (Automatically cleared by hardware after service begins.) (Note: Do not set START if DMA request comes from HW) active Status bit indicating the channel is currently in execution. done Status bit indicating major loop completion. (Set by hardware as CITER reaches 0. Cleared by software if using software initiated DMA service request.) d_req Control bit to disable DMA request at end of major loop completion. Clears channel enable bit, DMAERQ, at major loop completion so no additional DMA requests are recognized until channel is enabled again (Important for FIFOs – later)

eDMA: Other Control & Status Fields (2 of 2)
TCD Control Field Name Description BWC[0:1] Control bits for “throttling” bandwidth control of a channel. e_sg Control bit to enable scatter-gather feature. int_half Control bit to enable interrupt when major loop is half complete (DONE = 0) int_major Control bit to enable interrupt when major loop completes (DONE = 1) BWC - Bandwidth Control Forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar. 00 No DMA_Engine stalls (for inner loop) 01 reserved 10 DMA_Engine stalls for 4 cycles after each R/W 11 DMA_Engine stalls for 8 cycles after each R/W

eDMA: Summary 32-bit Source and Destination addresses
Source Address (saddr) Signed Source Address Offset (soff) Transfer Attributes (smod, ssize, dmod, dsize) Inner “Minor” Byte Count (nbytes) Last Source Address Adjustment (slast) Destination Address (daddr) Current Iteration Count (citer) and optional channel link control (citer.e_link, citer.linkch) Signed Destination Address Offset (doff) Last Destination Address Adjustment (dlast_sga) Channel Control & Status (bwc, linkch, done, active, e_link, e_sg, dreq, int_half, int_maj, start) “Major” Iteration Count (biter) and optional channel link control (biter.e_link, biter.linkch) Transfer Control Descriptor - 32-bytes of local memory. 32-bit Source and Destination addresses Transfer attributes selects the size increment/decrement options. Iteration (minor loop) counter – runs to zero every activation. To initiate a software DMA transfer, software must: set the “start” bit in TCD later clear the “done” bit in TCD DMASSTRT – DMA Set Start Request DMACDONE – DMA Clear Done Status SSTRTQ[6:0] CDONE[6:0] A write value of 15, sets corresponding Start bit in TCD_15 descriptor A write value of 15, clears corresponding Done bit in TCD_15 descriptor A value greater than 63 written will Set or clear Start and Done Bits, respectively

eDMA: Channel Arbitration
Fixed-Priority Arbitration Pro: Fastest latency for higher priorities. Prevents lower priority tasks from using too much DMA bandwidth in case of a high priority deadline. Con: Potential to use up DMA bandwidth if a channel is always active in highest priority group. Preemption: Normally transfers must complete before another channel can initiate a transfer Fixed priority allows one level of preemption Chan15 Chan14 Chan13 Chan12 Chan11 Chan10 Chan9 Chan8 Chan7 Chan6 Chan5 Chan4 Chan3 Chan2 Chan1 Chan0 Note: 0 is lowest priority Example: Fixed Chan. Arbitration Channel Linking Note: When the DMA executes a channel link, it sets the START bit of the target (link) channel. Then, the arbitration pipeline is flushed. At this point, the target channel is in the arbitration pool with all other channels requesting service. Arbitration occurs and the highest priority channel requesting service is selected to execute. Thus higher priority channels will not be starved.

Capture waveforms using eMIOS and DMA
Input Pulse-Width Measurement (IPWM) Mode – CBDR captures rising adges, CADR captures falling edges DMA is triggered on falling edges at CADR capture) DMA stores timing values (timebase is i.e internal counter) from CADR/CBDR into RAM Interrupt generation at the end of major loop PWM C1 Falling PWM C1 Rising PWM C2 Falling PWM C2 Rising PWM C3 Falling PWM C3 Rising PWM C4 Falling PWM C4 Rising PWM C5 Falling PWM C5 Rising PWM C6 Falling PWM C6 Rising PWM C7 Falling PWM C7 Rising PWM C8 Falling PWM C8 Rising saddr (source address) = eMIOS CADR register daddr (destination addr.) = start of memory queue nbytes = 4 bytes (minor loop size; # bytes per request) biter = citer = 8 (# minor loops in major loop) d_req = 0 (keep channel enabled after major loop) ssize = 16 bits (read 1 halfword per transfer) soff = 4 bytes (src. addr. increment after transfer) slast = 0 (no src. addr. adjustment when done) smod = 3 (wrap address after each minor loop) dsize = 16 bits (write 1 half word per transfer) doff = 2 bytes (add 4 to dest. addr after each transfer) dlast = -32 bytes (restart daddr to start when done) dmod = 0 (disbaled) Source 16 bit register eMIOS CADR register CBDR register . INT_MAJ Enable an interrupt when major iteration count completes.

Generate waveforms using eMIOS and DMA
Waveform Period is defined by timebase – Unified Channel in MCB period eMIOS is working in Double Action Output Compare Mode (DAOC) – CADR is programmed to trigger rising edge on timebase match, CBDR is programmed to trigger falling edge on timebase match FLAG is set on second match and triggers DMA to write next waveform falling & rising edges to CADR/CBDR Interrupt generation at the end of major loop PWM C1 Rising PWM C1 Falling PWM C2 Rising PWM C2 Falling PWM C3 Rising PWM C3 Falling PWM C4 Rising PWM C4 Falling PWM C5 Rising PWM C5 Falling PWM C6 Rising PWM C6 Falling PWM C7 Rising PWM C7 Falling PWM C8 Rising PWM C8 Falling saddr (source address) = start of memory queue daddr (destination addr.) = eMIOS CADR register nbytes = 4 bytes (minor loop size; # bytes per request) biter = citer = 8 (# minor loops in major loop) d_req = 0 (keep channel enabled after major loop) ssize = 16 bits (read 1 halfword per transfer) soff = 2 bytes (src. addr. increment after transfer) slast = -32 (restart saddr to start when done) smod = 0 (disbaled) dsize = 16 bits (write 1 half word per transfer) doff = 4 bytes (add 4 to dest. addr after each transfer) dlast = 0 bytes (disable) dmod = 3 (wrap address after each minor loop) Destination 16 bit register eMIOS CADR register CBDR register . INT_MAJ Enable an interrupt when major iteration count completes.

Getting Started with MPC560xB The Freescale Cup

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