1. iTOP LEPS Beam Test Analysis LYNN WOOD JULY 17, 2013 PACIFIC NORTHWEST NATIONAL LABORATORY

2. Topics LEPS Beam Test Summary iTOP Electronics Overview IRS3B ASIC Corrections Voltage Timing Current Analysis topcaf (software) Results Next Steps

3. LEPS Beam Test – June 4-20, 2013 Goal: end-to-end test with Full quartz bar including mirror and prism Full bar of PMTs and ASIC-based electronics Belle II DAQ-based readout (COPPER) Facility: LEPS beamline at SPring-8 2 GeV photon beams generated by backward Compton scattering of UV laser photons off 8 GeV synchrotron ring electrons Photons strike Pb target, produce e + /e - pairs that pass through detector

4. LEPS Configuration e + beam trigger from four counters  rate:30 kHz Trigger rate:10 Hz DAQ rate: 5 Hz Timing available from accelerator timing signals: ~24.3 ps Data taken at multiple angles of incidence and locations: Cos  = 0 (normal to bar) Cos  = 0.39, x = 0cm Cos  = 0.37, x = 20cm

5. iTOP Electronics Overview

6. Physical Layout One SCROD One ASIC One carrier board

7. ASIC Block Diagram Per channel: Single input 128 sampling cells (capacitors) 256 transfer cells 32768 storage cells 64 counters for digitization Per ASIC: Timing generator Ramp generator (for digitization)

8. Uncertainties In the ASIC: Voltage uncertainties Comparator response (32768 x 8 per channel) ADC counter rates (64 per channel) Response of sampling array (128 x 8 per channel) Possible difference in DC vs. AC response Input coupling and signal frequency content Timing uncertainties Overconstrained timing – overlap/gap between records Varying delays from sample-to-sample Bias voltage (and noise on bias voltage), temperature drift Feedbacks cannot currently compensate for small drifts Outside the ASIC: Clock shared in “columns” across boards – currently unterminated traces Path length differences in FPGA for different ASICs Crosstalk between channels

9. Comparator Response ADCs are Wilkinson-style ramp comparators Fires when ramp exceeds stored voltage Signals stored with DC offset to fit into ADC’s dynamic range Offset varies cell-to-cell = pedestal correction Comparator response is nonlinear Transfer function varies for each storage cell Examples here from IRS2 and TARGET5 ASICs (same comparator as IRS3B)

10. AC vs. DC response Transfer functions measured with DC inputs, but AC response may be different One example: persistence Voltage has some dependence on previous-stored voltage Will show “ghost” pulse for 1+ cycles Will also reduce pulse height Should primarily affect large pulses Example from PSEC3 chip at right

11. Input Coupling Multiple components: Amplifier bandwidth Coupling into ASIC sample cells Can depend on timing parameters of ASIC – how many sampling cells are currently connected Definite apparent gain in pulser data, but spectral content differs between laser and pulser data Corrections not the same Hard to measure gain without fixed- height samples Need calibration signals that look like MCP-PMT signals! LaserPulser

12. Overconstrained Timing Timing within each 128 samples controlled by delay line Timing controlled by bias on delay line Each 128 sample set started with input clock Incorrect biasing may end sample too soon (gap between samples) or too late (overlap between samples)

13. Sample-to-Sample Timing Uncertainties Delay lines stages can have varying delays between them Has strong impact on timing resolution Measurement method: Inject fixed-amplitude pulses at known time Use simple measurement to determine timing (threshold + interpolation) Significant structure seen Delay lines also dependent on noise on bias voltage, temperature Very difficult to recover (requires detailed knowledge of noise spectrum) Evidence is seen of bias voltage noise Evidence seen of temperature drift as well

14. Feedback Loops FPGA firmware contains several feedback loops to keep timing, voltages stable Evidence seen that sampling rate varies slightly at both smaller and larger scales Feedback loops in FPGA cannot compensate for small drifts

15. Outside the ASIC Channel-by-channel variation in t0 of up to several ns seen Clock lines shared by 4 ASICs (across 4 boards) Traces currently unterminated, may be causing distribution of start times Each time FPGA design goes through place-and-route, different delays get set for different signals Laser tests show ~2.1% crosstalk effect in MCP-PMT Currently removed by ADC cut, but investigation into separation by both ADC and time underway

16. Current Status of Calibrations Voltage: pedestal correction only Kurtis Nishimura working on proper gain correction Timing: Large-scale t0 corrections Sample-by-sample timing corrections Complete this list!

17. iTOP Analysis Framework (topcaf)

18. Pulser Data There are two sample buffers with a depth of 64 samples These need to be corrected for each ASIC (8 channels/ASIC) ASIC correction, so only one channel per ASIC was pulsed

19. Image Plots Mapping of x-y positioning to global channel number

20. Pulser Raw Image ASIC correction, so one channel per ASIC was pulsed 1 problematic SCROD during these runs (4 ASICs were affected)

21. Pulser Sample to Sample Corrections There are two sample buffers with a depth of 64 samples These need to be corrected for each ASIC (8 channels/ASIC) ‘Even’ buffer ‘Odd’ buffer

22. Pulser Sample to Sample Corrections Before correction, two obvious peaks appear After correction, single peak seen

23. Pulser Resolution One entry per ASIC in histogram (64 total) 4 ASICs with > 100 ns timing still investigating, but all row 0 col 2 ASICs – may be FPGA issue

24. Pulser Corrected Image Corrected image much cleaner, aligned properly

25. Laser Data At LEPS, laser injected into bar via fiber at far corner Resulted in very uneven coverage Left/right differences, hot spot, and almost no photons in lower PMTs Difference in arrival times at PMTs across the bar 4cm = ~193cm in quartz 2.54 m 0.45 m 2.58 m

26. Laser Image with Pulser Corrections Additional timing offsets from laser trigger delays and PMT/PMT wiring offsets

27. Laser Resolution Laser resolution after pulser corrections worse than pulser resolution (~140 ps vs. ~70 ps) Pulser Laser

28. Laser Resolution (time walk) Additional calibration of time walk due to varying amplitude required Currently just ad-hoc correction latest???

29. Laser Resolution (time walk) Ad-hoc correction recovers pulser timing in laser data (~90 ps)

30. Final Laser Image Clear image of laser wavefront reflecting More data processing needed to measure resolutions Investigating methods of recovering lower PMTs (256+)

31. Beam Image (cos θ = 0, x=0) Using ADC range cut Need proper gain calibration

32. Beam Image (cos θ = 0.39, x=-1.0 cm) ADC range cut, need proper adc amplitude calibration work is ongoing

33. Beam Image (cos θ = 0.37, x=20.0 cm) ADC range cut, need proper adc amplitude calibration work is ongoing

34. More on framework? MC details? Versions? Backgrounds?