1. 1 A 1.1V 150GHz Amplifier with 8dB Gain and +6dBm Saturated Output Power in Standard Digital 65nm CMOS Using Dummy-Prefilled Microstrip Lines M. Seo 1, B. Jagannathan 2, C. Carta 1, J. Pekarik 3, L. Chen 1, C. P. Yue 1 and M. Rodwell 1 1 Dept. of Electrical and Computer Engineering University of California, Santa Barbara 2 IBM, Burlington, VT 3 IBM, Crolles, France

2. 2 Outline Introduction “Dummy-Prefilled” Microstrip Line –Structure and Modeling Design and Simulation Measurement Results

3. 3 Beyond 100GHz: What Applications? Attenuation (dB/km) Frequency (GHz) O2O2 O2O2 H2OH2O H2OH2O 94GHz140GHz220GHz Communication –Outdoor, indoor Imaging (Passive, active) –Security –All-weather radar –Medical

4. 4 Beyond 100GHz: Why CMOS? Low-cost Low-power Large-scale Integration → Parallelism –Large monolithic phased array, imager. RF/mm-wave, IF/analog, DSP on a same die. –System-on-chip –Digital calibration of RF/analog circuit imperfections, process variations. –Reconfigurability and adaptability

5. 5 What Challenges in 150GHz CMOS Amp? Low available FET gain, Low Supply Voltage –Careful FET layout & sizing –Multi-stage Common-Source Modeling uncertainties –Simple matching topology with microstrip (MS) lines Automatic “dummies” alter MS-line characteristics –Propose “Dummy-prefilled” MS-line Characterization –Full 2-port on-wafer TRL calibration

6. 6 FET Layout Frequency (GHz) 100 200300 Maximum Stable Gain (dB) Parallel gate feed (PGF) Series gate feed (SGF) Finger design: Reduce R g,ext and C gd (W F =1um) Wiring multiple fingers: Parallel versus Series 10x1um/65n

7. 7 “Microstrip Line” in Nanoscale CMOS “Automatic” dummies/holes to meet metal density rules. Line capacitance increases –ΔC depends on E-field orientation → Anisotropic Direct E/M simulation nearly impossible Ground plane Signal Line

8. 8 Possible Shapes of Dummy Pre-fillers Signal Line dummies “LINE” dummies Parallel to current flow “LINE” dummies Perpendicular to current flow “SQUARE” dummies No preferred direction of current flow Signal Line

9. 9 Reducing Complexity in E/M Sim Signal Dummy-free uniform dielectric with adjusted diel. constant E/M simulation feasible by significantly reducing # of dummies WS E-field lines Dummy Pre-fillers ε ε’ε’ Successive dummy-layer substitution by parallel-plate capacitor simulation

10. 10 Line Inductance/Capacitance vs Fill Ratio 25% Fill W:S = 1:1 56% Fill W:S = 3:1 L per unit length (317nH/m w/o fillers) C per unit length (103pF/m w/o fillers) +17% +32%

11. 11 Ground Plane Construction Solid GND plane not allowed Put holes, and strap M1 & M2 Where current flow is uniform (e.g. under MS-line) Where current flow is not uniform (e.g. under bends, T-junction, radial stubs) M1 M2 via +

12. 12 THRU-REFL-LINE (TRL) Calibration (1) THRU (2) REFL (3) LINE Amplifier Test Half THRU 450um Reference plane REFL & LINE need not be accurately known Measurements normalized to the line impedance ΔLΔL (ΔL= 90 deg @center freq) (Open, short, etc)

13. 13 3-Stage 150GHz Amplifier: Schematic Half THRU Amplifier 30u/65n TL1TL2TL3TL4 M1M2M3 V1 V2V3 V4 All TL’s: Z 0 = 51.2 W=10u (25% fill) Radial stub No DC block: Forces V GS =V DS for M1 & M2, but eliminates loss and modeling uncertainties associated with DC-block cap FET size is chosen for low matching loss Radial stub for lower loss than quarter-wave TL

14. 14 FET Sizing constant-g circle (20mS) constant-Q circle S11 S22* (g22  g11) Small FET Large FET Conjugate input/output/inter-stage match with shunt tuning stubs only. Z0Z0

15. 15 Simulated 150-GHz Amplifier Gain S21 (dB) Frequency (GHz) Radial stub (45deg opening) Open-stub Z0=34, W=20u 0.65V1.1V AC short Open-stub Z0=51, W=10u ¼λ¼λ ¼λ¼λ P DC = 25mW

16. 16 Die Photograph Dummy-prefilled radial stub Dummy-prefilled MS-lines 640  m Reference planes 640  m Area = 0.4mm 2 (w pads) = 0.16mm 2 (w/o pads) Stack: 9 Cu + 1 Al Automatic dummies

17. 17 S-parameter Measurement Setup Probe Station 140-220GHz mm-wave heads 8510C VNA W/G Coax WR05IF/LO OML Inc.AgilentGGB Probes

18. 18 Can we trust the calibration? S11 LINE < -35dB S11 THRU < -40dB |S21 THRU | < 0.1dB Probe coupling < -40dB Repeatability issues –Probe placement –Probe contact resistance |S11 OPEN | < 0.2dB

19. 19 Prefilled MS-Line: Measurement -2.0dB/mm @140GHz -2.8dB/mm @200GHz E/M Sim. E/M Sim (8% error) |S21| (dB/mm) S21 Phase (deg) LINE standard 1mm-long Line

20. 20 Measured Amp. S-Parameters Frequency (GHz) S-parameter (dB) S21 S22 S11 meas S11 sim Meas Sim 0.65V1.1V Peak |S21|= 8.2dB P DC = 25.5mW 3dB BW= 27GHz

21. 21 S21 versus Current Density S21 (dB) Drain Current Density (uA/um) DC Power (mW) V 0.5~0.9V

22. 22 S21 @Higher Drain Bias (M3) V VV 1.1V V1=V2=V3<V4 0.5~0.9V

23. 23 Amplifier Stability Factor Frequency (GHz) Stability Factors Unconditionally stable over 140-200GHz. B1 > 0 K > 1

24. 24 Large-Signal Setup 20 GHz Signal Source x12 Freq. Multiplier WR05 Variable Attenuator Power Meter WR05- WR10 Power correction: Insertion calibration using W/G THRU & On-wafer THRU Virginia Diode Inc. Erikson Instruments. On-wafer DUT P IN = -20dBm ~ +15dBm Freq= 153GHz ~175GHz 0.2dB loss WR05 GGB probes

25. 25 Large-Signal Characteristics P out (dBm), Gain (dB) Power Added Efficiency (%) Peak PAE= 8.4% P sat = +6.3dBm oP 1dB = +1.5dBm 0.65V1.1V freq= 153GHz P DC = 25.5mW P in (dBm)

26. 26 Comparison of Measured S21 Frequency (GHz) S21 (dB) S21 from VNA Meas. S21 from Power Meas. VNA Measurement: Full 2-port TRL calibration Power Measurement: Insertion calibration

27. 27 Performance Summary Technology 65nm digital CMOS Topology 3-stage Common-source Center freq 150GHz 3dB BW 27GHz Peak Gain 8.2dB Input RL -7.4dB Output RL -13.6dB DC Power 25.5mW P 1dB +1.5dBm P sat +6.3dBm

28. 28 Conclusion Minimalistic Circuit Design Strategy “Design-rule Compliant” Transmission Line Structure and Modeling Linear/Power measurement up to 200GHz Highest frequency CMOS amplifier reported to date

29. 29 Acknowledgement IBM for chip fabrication and support OML Inc. This work was supported by the NSF under grants CNS-0520335 and ECS-0636621