1. © 2005, it - instituto de telecomunicações. Todos os direitos reservados. Automatic Analog Integrated Circuits Layout Generator 9 th Annual “HUMIES” Awards for Human-Competitive Results Genetic and Evolutionary Computation Conference (GECCO), 2012 Ricardo Martins, Nuno Lourenço, Nuno Horta IT / Instituto Superior Técnico, Lisbon, Portugal

2. 2 OUTLINE  Introduction and Motivation  A brief description of the submitted Work  R. Martins, N. Lourenço, N. Horta, “LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach”, Genetic and Evolutionary Computation Conference (GECCO) 2012, July 2012, Philadelphia, USA.  R. Martins, "LAYGEN II – Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation", Master thesis in Electrical Engineering, May 2012, IST, Lisbon, Portugal. (To be published by Springer)  Why our result is “Human-Competitive”  Why our result is the “best” entry 9 th Annual “HUMIES” Awards, GECCO | July 07-12, 2012, Philadelphia, USA

3. 3 Integrated Circuit 9 th Annual “HUMIES” Awards, GECCO | July 07-12, 2012, Philadelphia, USA [J. Goes et al, UNINOVA/CTS, 2011]

4. 4 Why Analog IC Design Automation? 9 th Annual “HUMIES” Awards, GECCO COMPUTER-AIDED DESIGN TOOLS  Digital:  Auto Synthesis;  Auto Layout;  Highly Reusable IP.  Analog:  Limited Auto Synthesis;  Limited Auto Layout;  Hardly Reusable IP. [Rob A. Rutenbar, 2010] Urgent need for CAD tools that Increase analog designers’ productivity and Reduce development cycles. | July 07-12, 2012, Philadelphia, USA In today’s ASICs, analog circuits establish the LINK between digital circuitry and the continuous-valued external world.

5. 5 Analog IC Layout Generation Task 9 th Annual “HUMIES” Awards, GECCO [CADENCE® Virtuoso Layout Editor] DIFICULTIES  Due to the lack of automation, designers keep exploring the solution space MANUALLY using traditional layout editors;  Iterative and ERROR-PRONE task;  Demanding design rules of the NANOMETER technologies;  NON-REUSABLE nature of analog IC layout.  Analog layout design is many technology nodes behind leading-edge digital. | July 07-12, 2012, Philadelphia, USA

6. 6  The designer avoids time-consuming traditional editors.  All the automatically generated layouts are validated in CALIBRE®, a main reference in the IC design industry. Automatic Layout Synthesis using LAYGEN II | July 07-12, 2012, Philadelphia, USA 9 th Annual “HUMIES” Awards, GECCO ANALOG DESIGNER AUTOMATICALLY GENERATED LAYOUT

7. 7 Automatically Generated by LAYGEN II [R. Martins et al, “Multi-Objective Multi-Constraint Routing of Analog ICs using a modified NSGA-II Approach”, SMACD 2012] Why our result is “Human-Competitive” 9 th Annual “HUMIES” Awards, GECCO (D) The result is publishable in its own right as a new scientific result. Handmade Layout [J. Goes et al, “A 1.2V 300µW second-order switched-capacitor Δ∑ modulator”,´ESSCIRC 2011] Automatically generated layouts compete with human-created solutions in terms of: ROBUSTNESS, QUALITY and GENERATION TIME. | July 07-12, 2012, Philadelphia, USA

8. 8 SIMULATIONS  SCHEMATIC (Without non- idealities of layout) Post-Layout:  HANDMADE  LAYGEN II Why our result is “Human-Competitive” (D) The result is publishable in its own right as a new scientific result.  Automatically generated results sent for fabrication for the ultimate ON-DIE comparison with human-created solutions. | July 07-12, 2012, Philadelphia, USA 9 th Annual “HUMIES” Awards, GECCO

9. 9 Why our result is “Human-Competitive” 9 th Annual “HUMIES” Awards, GECCO (E) The result is equal to or better than the most recent human-created solution to a long-standing problem. | July 07-12, 2012, Philadelphia, USA  Our approach beats the existing state-of-the-art solutions by:  Implementing a technology and specification independent approach;  General for any circuit class;  Fast, flexible and robust generation based on evolutionary optimization kernel;

10. 10 Design 1 Design 2 Design 3 Why our result is “Human-Competitive” 9 th Annual “HUMIES” Awards, GECCO Design 1 Design 2 Design 3 Area [µm²] -a0 [dB] (E) The result is equal to or better than the most recent human-created solution to a long-standing problem. | July 07-12, 2012, Philadelphia, USA Efficiency on retargeting for different SPECIFICATIONS SETUP TIME + AUTOMATIC GENERATION < 10 MINUTES

11. 11 Why our result is “Human-Competitive” 9 th Annual “HUMIES” Awards, GECCO AMS 350 nanometers UMC 130 nanometers | July 07-12, 2012, Philadelphia, USA Efficiency on retargeting for different TECHNOLOGIES (E) The result is equal to or better than the most recent human-created solution to a long-standing problem. DIFFERENT TECHNOLOGIES = DIFFERENT DESIGN RULES SETUP TIME + AUTOMATIC GENERATION < 10 MINUTES

12. 12 Why our result is “Human-Competitive” 9 th Annual “HUMIES” Awards, GECCO (G) The result solves a problem of indisputable difficulty in its field.  The solution space grows rampantly with the number of devices to place and wires to route, always considering technologies with strict design rules and several layers, which all together lead to a huge problem; | July 07-12, 2012, Philadelphia, USA  The designer can easily take HOURS to explore partially the solution space;  Retargeting operations performed handmade usually lead to partial or COMPLETE LOSS of the previous work.

13. 13 Why our result is the “best” entry 9 th Annual “HUMIES” Awards, GECCO  We solve real problems of a $300 billion industry;  The approach deals with a problem of indisputable difficulty, that is still solved manually by designers in the industry, in a time consuming and error-prone process;  LAYGEN II considers challenging nanometer technologies. We have published results and sent for fabrication for a 130 nanometer design process. “In October 2010, TI acquired a 200mm wafer fab in Chengdu, China.”  Technology node: TI’s 350 nanometer LBC5 Power BiCMOS [Texas Instruments] | July 07-12, 2012, Philadelphia, USA

14. 14 THANK YOU 9 th Annual “HUMIES” Awards, GECCO | July 07-12, 2012, Philadelphia, USA