1. Reporting and Analysis of IBM’s CPU Measurement Facility Data Philadelphia CMG September 14, 2012 Bill Shelden Bill.Shelden@PerfTechPro.com

2. Introduction CPU Measurement Facility Using the SMF 113 records Data from a 2097-706 (z10) Relative Nest Intensity Matching LSPR Workloads (LOW, AVG, HIGH) Data from a 2818-Y02 (z114) MIPS Reasonability Check CPU Capacity Planning Checklist Conclusions PerfTechPro Offer Topics

3. CPU MF - 2012 Update and WSC Experiences for SHARE Atlanta Final.pdf CPU MF Webinar Part 1 May 2 Final.pdf CPU MF Webinar Part 2 June 14 Final.pdf Peter.Enrico.Exploring.SMF113.and.CPU.Counters.pdf SA23-2260-02 The Load-Program-Parameter and the CPU-Measurement Facilities.pdf SA23-2261-01 IBM The CPU-Measurement Facility Extended Counters Definition for z10 and z196.pdf References

4. Introduced in z10 and later processors New facility that provides hardware instrumentation data for production systems Two Major components Counters Cache and memory hierarchy information SCPs supported include z/OS and z/VM Sampling Instruction time-in-CSECT New z/OS HIS started task Gathered on an LPAR basis Writes SMF 113 records New z/VM Monitor Records Gathered on an LPAR basis – all guests are aggregated Writes new Domain 5 (Processor) Record 13 (CPU MF Counters) records Minimal overhead Introduction - CPU Measurement Facility

5. Counters are cumulative Need to compute deltas between records Cut on the SMF accounting interval Not the RMF interval Records pertain to a specific LPAR Introduction – Using the SMF113 records

6. Data from a 2097-706 (z10)

7. Cycles Per Instruction

8. Level 1 Miss %

9. % of L1 Misses Sourced from Memory

10. Instruction Sourcing Profile (of L1 Misses)

11. Relative Nest Intensity

12. Some Definitions: L2LP = % from Level 2 Local cache (same book) L2RP = % from Level 2 Remote cache (different book) L3P = % from Level 3 cache L4LP = % from Level 5 Local cache (same book) L4RP = % from Level 4 Remote cache (different book) MEMP = % sourced from Memory RNI - Reflects the distribution and latency of sourcing from shared caches and memory For z10 EC and BC: RNI = (1.0*L2LP + 2.4*L2RP + 7.5*MEMP) / 100 For z196 / z114: RNI = 1.6*(0.4*L3P + 1.0*L4LP + 2.4*L4RP + 7.5*MEMP) / 100 Relative Nest Intensity

13. L1MP 0.75AVERAGE RNI<0.75LOW 3% 1.0HIGH 0.6<RNI<1.0AVERAGE RNI<0.6LOW L1MP>6%RNI>0.75HIGH RNI<0.75AVERAGE RNI-based LSPR Workload Decision Table

14. Matching LSPR Workloads (LOW, AVG, HIGH)

15. Data from a 2818-Y02 (z114)

16. Cycles Per Instruction

17. Level 1 Miss %

18. % of L1 Misses Sourced from Memory

19. Instruction Sourcing Profile (of L1 Misses)

20. Matching LSPR Workloads (LOW, AVG, HIGH)

21. RNI may be Load dependent

22. Relative Nest Intensity

23. MIPS Reasonability Check

24. From CPU Table (LOW RNI) GPP ‘MIPS’ = 5045.60 ‘MIPS’/GPP = 5045.60 / 6 = 841 ‘MIPS’/GPP For 9:59 AM which is a LOW RNI interval 3.54 Cycles per Instruction 4.4 Cycles per nanosecond (per GPP) 4.4 / 3.54 = 1.24 Instructions per Nanosecond 1.24 x 1,000,000,000 Instructions per Second 1.24 x 1000 = 1240 MIPS/GPP MIPS Reasonability Check

25. Collect CPU Measurement Facility Data for all ‘important’ LPARs For each LPAR: Determine RNI-based LSPR workload mix among LOW, AVG or HIGH Determine MIPS values for current and contemplated CPUs based on RITRs for RNI- based LSPR workload mix just determined Use IBM’s zPCR to account for specific LPAR configuration CPU Capacity Planning Checklist

26. Great insights into hardware and workload relationship RNI May be load dependent More accurate CPU capacity planning Conclusions

27. Send us some of your data: 24 hours of data RMF 70, 71, 72, 73, and 75s SMF 113s from one LPAR We will: Return a set of charts in a PDF Discuss your results on a WebEx Contact Bill Hart at bill.hart@perftechpro.com PerfTechPro Offer