1. GlueX Collaboration Meeting October 2-4, 2014 Trigger System Update R. Chris Cuevas Trigger Hardware/Firmware Status  Hardware Status  Performance Test Plan L1 Firmware Status Round Trip Latency Check Diagnostics/Monitoring  Summary

2. 2 Hardware Status Trigger Supervisor ( TS ) - Complete  No open issues  ‘3 rd ’ Trigger crate installed in U1-14 to support separate FDC-CDC DAq -TD boards must be swapped to TS crate when using global system DAq Trigger Supervisor Input/Output (TSIO) – Complete Rear transition board tested with Densishield cable from GTP Polarity of receivers was incorrect. Repaired in firmware. Global Trigger Processor ( GTP ) – Complete Testing continues and verification of CODA libraries with the latest firmware release is ongoing. GTP manual to be released to web site soon. (Ben, Bryan, D. Abbott)  CODA process runs on embedded Linux OS on the GTP  Interface through Ethernet for configuration and diagnostics William Gu Ben Raydo Bryan Moffit C. Cuevas

3. TI – TD Trigger Interface – Trigger Distribution – Complete Additional spares on site and tested SubSystem Processor ( SSP ) – Complete Signal Distribution ( SD ) – Complete Electronics group has 4 new spares 3 William Gu B. Moffit D. Abbott Hardware Status

4. Trigger Fiber Optics Trigger System Fiber Optics - Complete  System diagrams updated for Hall D  Patch cable labels updated  Thanks to Hall D group for installation help! 4 A. Stepanyan M. Taylor

5. 5 William Gu B. Moffit D. Abbott Hardware Status Electrical –Optical-Electrical Electrical-to-Optical converters have been installed in the Tagger area and the FCAL platform. (Highland Technology – V720) There is a single Optical-to-Electrical converter in the TS crate (V730) The transmit units (EO) convert NIM signals to optical Simple method to send diagnostic signals from these areas to the TS rack IN1 IN6 NIM Input Signals Tagger Area Rack T-2 TS Crate Rack U1-14 IN1 IN6 NIM Input Signals Six (6) ST FO Connectors Six (6) ST FO Connectors FCAL Platform Rack D2-1(TOF) Only 6 FO INputs FO Trunk Line OUT1 OUT6

6. Crate Trigger Processor Firmware VXS Connectors Collect serial data from 16 FADC-250 (64Gbps ) Hai Dong Jeff Wilson B. Moffit A. Somov 2013 Production CTP New Front Panel I/O 6 Crate Trigger Processor ( CTP ) - Complete Production quantities (30) for Hall D All production boards pass (FCAT) Full Crate Acceptance Testing -CTP boards delivered to Hall D group Custom firmware for FCAL and BCAL energy sum and pedestal subtraction are tested with CODA libraries. CTP  SSP fiber link ID firmware feature is complete. Custom trigger firmware for: TAGM TAGH PS ST are complete and are in the final stage of test verification with latest CODA libraries. MTP Parallel Optics 8 Gbps to SSP Hardware Status

7.  Flash ADC 250Msps ( FADC250 ) - Production board delivery to JLAB groups is complete Production board repairs are progressing. (Only 8 more Hall D boards to repair!)  Bryan Moffit’s DAQ site contains the latest Jlab Module Manuals with notes for relevant firmware version and CODA libraries. https://coda.jlab.org/wiki/index.php/JLab_Module_Manuals -Firmware change request method seems to be working well. 1.Submit request to Hall D DAQ person 2.Hall D DAQ person sends to FE and DAQ group leaders 3.FE/DAQ groups will prioritize and organize relevant discussion meetings as required. 7 Trigger Hardware Status F. Barbosa H. Dong E. Jastrzembski Jeff Wilson

8. Round Trip Trigger Latency Check 8 Ben Raydo William Gu B. Moffit A. Somov

9. 9 Performance Testing Measured in the lab, need to measure in the Hall next?

10. Performance Testing What’s next? Activity 2543115 – Performance Testing Establish trigger distribution connections (Fiber) to all crates Global Crate o Establish CTP  SSP fiber link connections o Initial GTP and TS Trigger functions appear to work well o 2 nd TS crate added for FDC and CDC for independent readout Is this a permanent solution? o Limited high rate testing accomplished with TOF, Global and TS crates Cosmic Ray trigger testing successful FCAL, BCAL, TOF BCAL with FDC and CDC -TAGH crate remains in the Tagger area for another week 10

11. Activity 2543115 – Performance Testing  Trigger system hardware design goals need to be tested and verified  The CODA/DAq/Network/EB/ET hardware and software testing ran into issues, so there may not be enough time before 1 st beam to fully test the Trigger system at design goal rates. (200KHz)  High rate (>10KHz?) not required for initial beam commissioning in the next month. 11 Performance Testing What’s next?

12. Activity 2543115 – Performance Testing  Firmware features and tools exist to fully test the front end hardware and trigger modules without detector signals. -- Test procedure { Use ALL DAq crates }  Use “Playback” mode to simulate low or high occupancy in FADC250 crates.  Configure readout mode for Integral value. [Reduce data size per trigger]  Configure BUSY assertion level in FADC250 crates  Configure L1 CTP boards for Energy Sum, or Bit-Patterns  Use TS to produce TRIG2 command at random rate. -TRIG2 is used to start the “Playback” waveform -Use TRIG2 to test rate up to 200KHz  VERIFY  Trigger counters – All boards, All crates  Clock counters – All boards, All crates  Sums and Bit-Patterns should be deterministic and align without issue  Test duration - How long will the system remain error free? - At what rate does the system become unstable? 12 Performance Testing What’s next?

13. Activity 2543115 – Performance Testing  Would be nice to have expert ‘screens’ for diagnostics of Trigger boards. - Every board has FPGA temperature and voltage registers for readout - May be a good idea to log these at a slow rate (back round process?)  Other diagnostic tools that will prove very useful in the future should use small scale DAq/Trigger setups that include the TS-TD crate, Global Crate and a single L1 crate. - This type of 3 crate tool would use “Playback” data to quickly run deterministic Trigger testing and verify that all timing, FO links, Gigabit Serial transport hardware is functioning properly. 13 Performance Testing What’s next?

14. Summary All Global Trigger and Trigger Distribution hardware installed All Trigger FO trunk lines are installed and tested Firmware released for all boards is stable - Final testing and verification in progress for CTP applications Essential CODA library development and library release is complete for almost every board. GTP still going through final iterations. High rate performance testing still needs to be completed and documented -Tools for “Playback” mode testing exist 12GeV Trigger hardware meetings have concluded, but meetings for specific trigger application development in each Hall will continue. Questions? 14

15. All sorts of cool stuff

16. All Trigger Modules Delivered! 2 Front End Crate FADC250, (FADC125), (F1TDC) Crate Trigger Processor Signal Distribution Trigger Interface Trigger Control/Synchronization Trigger Supervisor Trigger Distribution L1 Trigger ‘Data’ MTP Ribbon Fiber Trigger ‘Link” Control Clock, Sync MTP Ribbon Fiber Global Trigger Crate Sub-System Processor Global Trigger Processor

17. Full DAq Crate Testing Plans 17 Before deploying full crates with all required modules: Will test using “Playback” mode and CODA No input cables necessary; User defined signals loaded in front-end FPGA Deterministic test for all channels and Gigabit serial lane alignment check Verify TI  SD  Payload Board Synchronization and Clock Re-Use these tools for Hall commissioning effort Test station used for FINAL firmware verification and software ‘library’ development Bryan Moffit has created a preliminary plan and list of test functions See wiki link  https://halldweb1.jlab.org/wiki/index.php/Full_Crate_Acceptance This full crate test station in EEL109 is an essential infrastructure element needed to test and verify the front end and trigger hardware/software before installation in the Halls. Bryan Moffit Et al.

18. System Description Crate Trigger Processing Flash ADC Modules Detector Signals Sub-System Processing (Multi-Crate) Global Trigger Processing Trigger Supervisor (Distribution) TS -> TD -> TI Link 1.25Gb/s Bi-Directional BUSY Trigger Sync Trig_Comnd CTP -> SSP -> GTP L1 Trig_Data Uni_Directional Energy Sums 6

19. Noise in the FADC (No Readout during data taking) 03/21/2012CniPol Meeting 19 Single Event All Events

20. Noise in the FADC (Readout during data taking) 03/21/2012CniPol Meeting 20 Single Event All Events

21. Two DAQ Crate Testing: FY11 200KHz Trigger Rate! Pre-Production and 1 st article boards have been received and tested Significant effort for circuit board fabrication, assembly and acceptance testing System testing includes: Gigabit serial data alignment 4Gb/s from each slot 64Gb/s to switch slot Crate sum to Global crate @8Gb/s Low jitter clock, synchronization ~1.5ps clock jitter at crate level 4ns Synchronization Trigger rate testing Readout Data rate testing Bit-Error-Rate testing - Need long term test (24 - 48 hrs) Overall Trigger Signal Latency ~ 2.3us (Without GTP and TS) Readout Controller Capable of 110MB/s - Testing shows we are well within limits