1. Nishinaga No. 1 MAPLD2005 Availability Analysis of Xilinx FPGA on Orbit Nozomu Nishinaga National Institute of Information and Communications Technology Masayoshi Yoneda NEC TOSHIBA Space Systems, Ltd.

2. Nishinaga No. 2 MAPLD2005 Outline  Motivation  Heavy Ion test results of Virtex II pro  Availability analysis  Conclusion

3. Nishinaga No. 3 MAPLD2005 Motivation  Very high availability or low non-availability is required for the consumer communications equipment.  typical non-availability value for terrestrial network equipment is 10E-6  If the SEU can be defined as an accidental failure and the failure can be fixed without any loss of the original device function.  the rebooting process also can be defined as a repairing  Does equimpment with S-RAM type FPGAs meet the non-availability criteria?

4. Nishinaga No. 4 MAPLD2005 Radiation test of Virtex II Pro  Virtex II pro (XC2VP7-5FG456 and XC2VP4)  Test carried out in November 2003 and February 2004 at TIARA in Takasaki, Japan  Heavy Ions (N, Ne, and Kr)  Result compared with that of Virtex II. (Gary Swift, Candice Yui, and Carl Carmichael,” Single-Event Upset Susceptibility Testing of the Xilinx Virtex II FPGA,” MAPLD2002, paper P29)

5. Nishinaga No. 5 MAPLD2005 Devices Under Testing XC2VP4XC2VP7XC2VP100 Configuration Memory3.01 [Mbit]4.49 [Mbit]34.29 [Mbit] DCM (Digital Clock Manager) 4 [unit] 12 [unit] Block RAM 28 [unit]44 [unit]7992 [kbit] F/F 6016 [unit]9856 [unit] Multiplier 28 [unit]44 [unit] Rocket I/O 4 [Block]8 [Block]

6. Nishinaga No. 6 MAPLD2005 Radiation test result (1) Block RAM region 1E-11 1E-10 1E-09 1E-08 0.0000001 0.000001 010203040506070 LET[Mev cm^2/mg] Cross Section [cm^2/bit] XC2VP4 XC2VP7 Virtex-II

7. Nishinaga No. 7 MAPLD2005 Radiation test result (2) Configuration Memory region

8. Nishinaga No. 8 MAPLD2005 SEU frequency analysis (CREAM 96) Solar MAXFlare Peak (1 week) Conf. Memory 0.33 times/day163.4 times/day DCM 0.00 times/day 0.11 times/day Block RAM 0.04 times/day21.87 times/day Multiplier 0.00 times/day 0.46 times/day XC2VP4 Solar MAXFlare Peak (1 week) Conf. Memory 0.49 times/day243.8 times/day DCM 0.00 times/day 0.11 times/day Block RAM 0.07 times/day34.4 times/day Multiplier 0.00 times/day 0.72 times/day XC2VP7

9. Nishinaga No. 9 MAPLD2005 Mean Time Before Failure Analysis  If the SEU can be considered as A Failure, the MTTR is roughly proportional to the size.  System MTBF -> Harmonic Mean of all functional blocks  Assumption 1: All the SEUs can be detected.  Assumption 2: All the gates are used.  Assumption 3: All the SEUs must be repaired as soon as quickly XC2VP4XC2VP7XC2VP100 (Simulated) Solar MAX (Sec.) Flare Peak (1 week) (Sec.) Solar MAX (Sec.) Flare Peak (1 week) (Sec.) Solar MAX (Sec.) Flare Peak (1 week) (Sec.) Conf. Memory 2.64E+055.29E+021.77E+053.55E+022.32E+044.64E+01 DCM 4.14E+088.09E+054.14E+088.09E+051.38E+082. 70E+05 Block RAM 2.02E+063.95E+031.28E+062.51E+031.27E+052.49E+02 Multipliers 7.89E+071.89E+055.02E+071.21E+054.98E+061.19E+04 SYSTEM2.3267E+054.6495E+021.5501E+053.0972E+021.95E+043.90E+01

10. Nishinaga No. 10 MAPLD2005 Mean Time To Repair (MTTR)  REBOOT == Repair  The effects of SEU are volatile.  By loading the correct configuration data, the operation mode will go to the normal mode.  Rebooting time -> Repair time  The maximum data rate for loading is fixed : 50M byte/Sec. for XC2VP series.  The larger gate size or configuration size, the longer MTTR becomes necessary. XC2VP4XC2VP7XC2VP100 Configuration data (bit)3,006,5604,485,47234,292,832 MTTR (s) (10Mbyte/s)0.0375820.0560680.42866 MTTR (s) (50Mbyte/s)0.0075160.0112140.085732

11. Nishinaga No. 11 MAPLD2005 Triple Module Redundancy Case 1: One out of Three system failure is acceptable.  Loose regulation  Acceptable when the MTBF is quite large compared with MTTR Case 2: NO failure is acceptable  Tight configuration  The output is always guaranteed.

12. Nishinaga No. 12 MAPLD2005 Non-Availability Alalysis  MTBF is proportional to the area of the die and MTTR is also proportional. -> Large FPGA has disadvantage.  Large size FPGA does not meet the criteria 10e-6  How to mitigate? – divide small FPGAs  Much larger down load rate will be needed (50 M Byte/S is too slow) Case 2XC2VP4XC2VP7XC2VP100 (Simulated) Solar MAXFlare PeakSolar MAXFlare PeakSolar MAXFlare Peak 10Mbyte/s4.85E-072.42E-041.09E-065.43E-046.59E-053.23E-02 50Mbyte/s9.69E-084.85E-052.17E-071.09E-041.32E-056.57E-03 Case 1XC2VP4XC2VP7XC2VP100 (Simulated) Solar MAXFlare PeakSolar MAXFlare PeakSolar MAXFlare Peak 10Mbyte/s7.83E-141.96E-083.93E-139.83E-081.45E-093.53E-04 50Mbyte/s3.13E-157.84E-101.57E-143.93E-095.79E-111.44E-05

13. Nishinaga No. 13 MAPLD2005 Dividing  The Non-Availability depends on the size  A Large size FPGA is split up to several (D) small FPGAs  S c -> Configuration data size [bits]  R -> Configuration rate [bps]

14. Nishinaga No. 14 MAPLD2005 Interstage VOTER  The availability is varying With or Without the interstage Voter.  The performance with interstage voters is superior to tat without the voters.

15. Nishinaga No. 15 MAPLD2005 Non-Availability Analysis with dividing Area or gate loss due to the division is not taking into account in this figure. -> next issue

16. Nishinaga No. 16 MAPLD2005 Conclusion  Non availability analysis for Vertex II pro  Large scaled FPGA do not meet a non availability criteria for communication equipment (10e-6).  Need much faster or wider Interface for configuration to enhance its availability.