1. Results of the ASIC Test New Developments Next Steps Project Meeting

2. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 2 Results of the ASIC Test Delivery Date of ASIC: 14. August 2014 Delivery Date of Hybrid Board: 27. August 2014 Start Measurements: 1. September Check of all Functionalities Timing Fast Trigger Slow Trigger of 1. Row Readout Hit Matrix Using Test Pads v v v v

3. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 3 Test Setup Installation and Preparation of Test Software was done by the summer student Alessio Borgheresi (22.07.-11.09.) Mainboard Hybrid-Board with Test ASIC

4. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 4 Loading of the Status Control Register via NI Labview Possibility for Enabling the individual Pixel to stimulate the Sensors Output

5. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 5 Timing Test Concept Trigger Latch Reset FF Out FF Out Dummy TestIn FF FF- Dummy DUT TestIn Latch Trigger Latch n∙∆t tdtd tdtd ∆t N∙∆t 0.5 1 0 Event histogram of FF Out and FF Out Dummy Entries (a.u.)

6. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 6 Timing Test Results, randomly activated Pixels VDD = 1.2 V VDD2 = 3.3 V ?

7. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 7 Timing Test Results, Variation of Supply Voltages

8. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 8 Timing Test Results, Corner Variation (simulated, 1.2 V)

9. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 9 Timing Test Results, extending Circle VDD = 1.2 V VDD2 = 3.3 V

10. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 10 Timing Test Results, extending Point VDD = 1.2 V VDD2 = 3.3 V

11. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 11 New Developments > Timing Improvements in the Front-End Electronics  Faster by 250 ps > Design of global Blocks (Sequencer, Controller and Multiplexer)  Digital approach  External Signals: Bunch Clock, System Clock, Start/Select > Improvements on Slow-Trigger performance  Consideration of all process corners via extra Switch

12. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 12 Next Steps > ASIC + (SiMPI-)Sensor Test Space for 6x6 mm² Sensor Chip > Sending ASICs to PacTech

13. DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 13 End > Thank you! Project Wiki-Page: fec-sipm.desy.de