1. 28/10/2007DSD,USIT,GGSIPU1 Latch & Register Inference

2. 28/10/2007DSD,USIT,GGSIPU2 Latch Inference In non-clocked processes, incompletely specified if and case statements cause synthesizers to infer latches for the variables and signals being assigned.

3. 28/10/2007DSD,USIT,GGSIPU3 Example --data_out is a latch Process(somesignal) Begin if (somesignal=‘1’) then data_out<= data_in; end if; End process; Process (somesignal) Begin case somesignal is when ‘0’ => data_out<= data_in; End case; End process; A latch is inferred for the signal data_out because is not assigned under all possible conditions. If the tested condition fails then data_out must hold the previous value.

4. 28/10/2007DSD,USIT,GGSIPU4 Definition Basic Latch is a feedback connection of two NOR gates or two NAND gates, which can store one bit of information. It can be set to 1 using the S input and reset to 0 using the R input. Gated Latch is a basic latch that includes input gating and a control input signal. The latch retains its existing state when the control input equals to 0. Its state may be changed when the control signal is equal to 1.

5. 28/10/2007DSD,USIT,GGSIPU5 Definition (cont..) Flip Flop: A flip flop is a storage element based on the gated latch principle, which can have its output state changed only on the edge of the controlling clock signal. Two types of FF: –Edge Triggered FF –Level triggered FF

6. 28/10/2007DSD,USIT,GGSIPU6 VHDL code for gated D-FF entity dff is Port ( d : in std_logic; clk : in std_logic; reset: in std_logic; q : out std_logic); end dff; architecture Behavioral of dff is begin process(clk,reset) begin if (reset ='1') then q <= '0'; elsif (clk'event and clk='1') then q <= d;end if; end process; end Behavioral;

7. 28/10/2007DSD,USIT,GGSIPU7 Waveform of D-ff

8. 28/10/2007DSD,USIT,GGSIPU8 Register A flip-flop stores one bit of information. When a set of n flip-flops is used to store n bits of information, such as an n-bit number, it is called Register. A common clock is used for each flip-flop in a register.

9. 28/10/2007DSD,USIT,GGSIPU9 A simple shift register

10. 28/10/2007DSD,USIT,GGSIPU10 Shift Left Register entity shifleft is Port ( newdata : in std_logic; datain : in std_logic_vector(3 downto 0); dataout : out std_logic_vector(3 downto 0); clk : in std_logic; reset : in std_logic); end shifleft; architecture Behavioral of shifleft is begin process (clk,reset,newdata) begin if (reset='1') thendataout <= "0000"; elsif (clk'event and clk='0') then dataout <= datain(2 downto 0) & newdata; end if; end process; end Behavioral;

11. 28/10/2007DSD,USIT,GGSIPU11 Waveform of Shift Left

12. 28/10/2007DSD,USIT,GGSIPU12 VHDL code for Right Shift Register entity shiftReg is Port ( datain : in std_logic_vector(3 downto 0); newdata : in std_logic; dataout : out std_logic_vector(3 downto 0); clk : in std_logic; reset : in std_logic); end shiftReg; architecture Behavioral of shiftReg is begin process(clk,reset) begin if (reset ='1') thendataout <= "0000"; elsif (clk'event and clk='0') then dataout <= newdata & datain(3 downto 1); end if; end process; end Behavioral;

13. 28/10/2007DSD,USIT,GGSIPU13 Waveform of shift Right register

14. 28/10/2007DSD,USIT,GGSIPU14 VHDL code for shift register entity shiftRegester is Port ( reset,clk,w : in std_logic; q : out std_logic_vector(3 downto 0)); end shiftRegester; architecture Behavioral of shiftRegester is signal temp : std_logic_vector(3 downto 0); begin process(clk,reset) beginif (reset ='0') then q '0'); elsif (clk'event and clk='1') then genbits: for i in 3 downto 1 loop temp(i) <= temp(i-1); end loop; temp(0) <= w; end if; q <= temp; end process; end Behavioral;

15. 28/10/2007DSD,USIT,GGSIPU15 Waveform of shift register

16. 28/10/2007DSD,USIT,GGSIPU16 Serial-in Serial-out Shift Register

17. 28/10/2007DSD,USIT,GGSIPU17 Serial in Parallel out

18. 28/10/2007DSD,USIT,GGSIPU18 counter entity counterUP is Port ( clk : in std_logic; load: in std_logic; d : in std_logic_vector(3 downto 0); reset : in std_logic; e : in std_logic; q : out std_logic_vector(3 downto 0)); end counterUP;

19. 28/10/2007DSD,USIT,GGSIPU19 architecture Behavioral of counterUP is signal count: std_logic_vector(3 downto 0); begin process(clk,reset,load,d) begin if (load='1') then count <= d;-- loadable counter elsif (reset='0') then count <= "0000"; elsif (clk'event and clk='0') then if (count="1001") then-- decade counter count <= "0000" ; elsif (e ='1') then count <= count + 1; else count <= count - 1; end if; end process;q <= count; end Behavioral;

20. 28/10/2007DSD,USIT,GGSIPU20 Waveform of counter design