1. Electronic Systems Design Group School of Electronics and Computer Science University of Southampton, UK A CAD Methodology for Switched Current Analog IP Cores Bashir Al-Hashimi bmah@ecs.soton.ac.ukrw01r@ecs.soton.ac.uk Reuben Wilcock

2. University of Southampton, UK Slide 2 Outline Introduction Two part CAD methodology Switched current wave filters Applying the CAD methodology Example filter design Summary

3. University of Southampton, UK Slide 3 Introduction System on Chip –Analog IP cores are a difficult issue The switched current technique –Relies on Cgs to maintain drain current –Analog functions implemented with only transistors –Current mode allows low Vdd –Perfect for present and future digital processes Problem: lack of tools and design experience Solution: Hierarchical cell library and SKILL® based CAD tool

4. University of Southampton, UK Slide 4 Each core is supported with hierarchical library –Top level symbols –Ideal models –BSim3v3 Hierarchical cell library Design Reuse Hierarchy pPar() Design variables

5. University of Southampton, UK Slide 5 SKILL ® based CAD tool SKILL ® CAD tool guides the core design flow –Driven by underlying equations –Ideal high level design through to transistor level –Multi-level optimisation

6. University of Southampton, UK Slide 6 Wave filters emulate passive filters [Fettweis ’86] L and C transformed into positive and negative delays Series and parallel adaptor blocks connect L and C Ideal for switched current implementation Wave filter core design

7. University of Southampton, UK Slide 7 Wave filter cell library Entire cell library for wave filter cores Ideal and behavioural models for high level Transistor level circuits for low level Library spans from top core to BSim3v3 models Many filter types orders and functions supported

8. University of Southampton, UK Slide 8 Wave filter CAD tool Integration into Cadence allows interactive design Passive filter design Wave filter design and optimisation Memory cell design and optimisation Entire transistor level filter verification

9. University of Southampton, UK Slide 9 Example flow: Step 1 De-normalise values Frequency response Choose filter type/function/order Normalised component values

10. University of Southampton, UK Slide 10 Example flow: Step 2 Optimise [Yufera ’94] Frequency response from behavioural models Decide cutoff/sample ratio Coefficients are calculated

11. University of Southampton, UK Slide 11 Example flow: Step 3 S 2 I memory cell [Hughes ’00] Trade off design parameters First cut design calculated DC, transient simulations Optimise for gm, Cgs, Ctot, Switch Ron and settling

12. University of Southampton, UK Slide 12 Example flow: Step 4 Save all design variables, dimensions and coefficients to a single file Schematic representing entire transistor level design is opened Spectre RF used to give an AC response in minutes Revisit steps 1 – 3 as necessary

13. University of Southampton, UK Slide 13 Silicon case study Case study taken to silicon to verify methodology –Elliptic Lowpass –3 rd order –1M sample/sec –1:10 cutoff ratio Process –0.6  m –3.3V supply –Single poly –0.7mm 2

14. University of Southampton, UK Slide 14 Silicon results Excellent preliminary silicon results

15. University of Southampton, UK Slide 15 Summary

16. University of Southampton, UK Slide 16 Contact Reuben Wilcock Electronic Systems Design Group School of Electronics and Computer Science University of Southampton United Kingdom rw01r@ecs.soton.ac.uk