1. Compensation for Measurement Errors Due to Mechanical Misalignments in PCB Testing Anura P. Jayasumana, Yashwant K. Malaiya, Xin He, Colorado State University Kenneth P. Parker and Stephen Hird Agilent Technologies

2. Objective 2 Identification of outlier boards using Capacitive Lead Frame Testing data Improve the accuracy of outlier detection by compensating for systematic errors such as mechanical misalignment and fixture-to-fixture variations BTW 2010

3. Outline  PCA Based Outlier Detection  Test Data for Mechanical Misalignments  PCA Based Compensation  Summary 3 BTW 2010

4. Capacitive Lead Frame Testing 4 Ref: Parker & Hird, ITC 2007 BTW 2010

5. Example: Capacitance vs. Pin Number (for a J245) 5 BTW 2010

6. 6  1 st Principal Component contains largest variance from the data projection  2 nd Principal Component, orthogonal to the 1 st one, contains second largest projected variance  Useful for analyzing multi- dimensional interrelated data Measurement 2 2 nd PC 1 st PC 0 Measurement 1 Principal Component Analysis (PCA) BTW 2010

7. PCA for PCB Outlier Detection 7 M McMcMcMc Let M be (mxn) matrix of Capacitive Lead Frame Testing measurements - m is the number of boards - n is number of tested pins per board Centering BTW 2010

8. PCA for PCB Outlier Detection M c = USV T Singular Value Decomposition M c = USV T where, U mxn A scaled version of PC scores S nxn Diagonal matrix with square roots of Eigen values in descending order V T nxn Eigen vectors (PCs). V Transformation Matrix Z = M c V Z = M c V Matrix with z-score values of boards Z-scores of a board are linear combination of all corresponding measurements for that board 8 BTW 2010

9. Test Statistic for Outlier Detection 9 z ik : Value of the k th PC for i th board E : a subset of PCs - most significant PCs are used here  Sort the boards with respect to d 1  Plot cumulative distribution function (CDF) of d 1  Outliers clearly identifiable on right side of plot, typically separated from others by a clear margin BTW 2010

10. 10 Board run numbers on CDF plot from left to right: 52,51,50,53,49,32,73,24,48,25,74,72,83,71,57,47,1,42,56,70,6,68,38,37,58,43,59,41,39, 55,40,2,23,78,33,35,44,69,79,54,75,36,64,80,76,31,77,65,60,29,81,63,61,62,3,67,66,82, 27,45,28,46,26,30,34,12,8,7,10,9,16,11,13,14,15,4,5,17,22,19,18,20,21 PCA Based Outlier Detection ITC 2009 Treats data holistically Outlier detection as opposed to threshold based detection

11. Capacitive Lead Frame Testing 11 Ref: Parker & Hird, ITC 2007 Capacitance < 100fF (<10fF with opens faults) Systematic variations, e.g., variations in connector height, co-planarity of ball connections, sense plate, … Relatively small mechanical variations can lead to larger measurement variability (Ex. 18fF variation across shift test cases vs. std deviation of <1fF) Test values and test limits set now may fail if mechanical variations appear later BTW 2010

12. Mechanical Misalignments 12 Setup Left or right End Tilt Height (mils) Setup Vertical Shift Height (mils) Tilt_00Shift_00 Tilt_18Shift _18 Tilt_216Shift_216 Tilt_324Shift_324 BTW 2010

13. Raw measurements for B1 with one normal and three left tilted sense plates Tilt_0 Tilt_1 Tilt_2 Tilt_3 BTW 2010

14. Raw measurements with normal and vertical shifted sense plate for board B5 connector J3 Shift_0 Shift_1 Shift_2 Shift_3 BTW 2010

15. Compensating for Tilt 15 BTW 2010

16. Raw measurements with normal and vertical shifted sense plate for board B5 connector J3 Shift_0 Shift_1 Shift_2 Shift_3 BTW 2010

17. Plot of PC values for Shift Data Note: PC-1 can be used to identify the amount of shift or tilt in sense plate Unlike visual inspection, PCA can identify complex but systematic patterns If the same board is tested in multiple fixtures, it may be possible to identify differences and compensate for them BTW 2010

18. Adjusted capacitances by setting all but 1st PC equal to 0 for data B1 PC-1 captures the tilt information as well as other common information BTW 2010

19. Data set including two synthetic traces, Def_1 and Def_2 simulating open faults on pins 121 and 165 BTW 2010

20. Adjusted capacitances by setting only 1st PCs to 0 BTW 2010

21. Data set including two synthetic traces, Def_1 and Def_2 simulating open faults on pins 75 and 165 BTW 2010

22. Adjusted capacitance by setting all but 1st PC to zero BTW 2010

23. Adjusted data based on setting only 1st PC to 0 BTW 2010

24. 24  A PCA based technique presented for identification and compensation for measurement errors introduced due to sense-plate variations  Method can be used to separate misalignment related information from defect related information in test data  Approach is NOT sensitive to the order of the pins, and thus shows promise for complex but systematic errors introduced by sense plate misalignments  Method applicable to other kinds of test data Summary BTW 2010

25. 25  Overcome variations caused by measurement errors, mechanical and electrical tolerances  Adaptive and learning techniques for detection and diagnosis Future Work BTW 2010