1. 1 A Random Access Scan Architecture to Reduce Hardware Overhead Anand S. Mudlapur Vishwani D. Agrawal Adit D. Singh Department of Electrical and Computer Engineering Auburn University, AL 36849 USA

2. 2 Motivation for This Work Serial scan (SS) test sequence lengths and power consumption are increasing rapidly. –Reduction of test power and test time are complimentary objectives in serial scan. Scope of increasing delay fault coverage is limited in serial scan. In spite of the three advantages (test time, power, and delay fault coverage) random access scan (RAS) is not popular due to high overhead.

3. 3 Outline Introduction Review of our “toggle” Flip-Flop design Highlight the uniqueness and feasibility of our design due to the reduction of two global signals A new scan-out structure Results on ISCAS Benchmark Circuits Conclusion

4. 4 Introduction Random Access Scan (RAS) offers a single solution to the problems faced by serial scan (SS): –Each RAS cell is uniquely addressable for read and write. –RAS reduces test application time and test power which are otherwise complimentary objectives. Previous and current publications on RAS: Ando, COMPCON -80 Wagner, COMPCON -83 Ito, DAC -90 Baik et al., VLSI Design -04, ITC -05, ATS -05, VLSI Design -06 Mudlapur et al., VDAT -05 Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flip-flops.

5. 5 Contributions of Present Work Eliminate scan-in signal from circuit by using a toggling RAS flip-flop. Eliminate routing of test control signal to flip-flops. Provide a new scan-out architecture: –A hierarchical scan-out bus –An option of multi-cycle scan-out

6. 6 Serial Scan (SS) Example:A circuit with 5,000 FFs and 10,000 combinational test vectors Total test cycles = 5,000 x 10,000 + 10,000 + 5,000 50,015,000 = 50,015,000 Combinational Circuit FF Scan-inScan-out PIPO Test control (TC)

7. 7 Random Access Scan (RAS) During every test, only a subset of all Flip-flops needs to be set and observed for targeted faults Combinational Circuit FF PIPO Scan-out bus bus Decoder AddressInputs Scan-in TC These signals are eliminated in our design

8. 8 The “Toggle” RAS Flip-Flop MS Clock MUXMUX Combinational Logic Data Row Decoder Column Decoder Combinational Logic Data Logic Data To Output BUS Address (log 2 n ff ) y x √n ff Lines RAS-FF 0 1 OutputBUSControl

9. 9 Toggle Flip-Flop Operation FunctionClock Address decoder outputs Row (x)Column (y) Normal DataActive00 Toggle Data Inactive1Active Clock InactiveActive Clock1 Hold Data Inactive10 01 00

10. 10 Toggle Flip-Flop Operation (contd.) RAS FF 1 Unaddressed FFs Addressed FF RAS FF 0 Decoded address lines RAS FF 0 RAS FF 1 x4 y1 y2 y3

11. 11 Macro Level Idea of Signals to RAS-FF x1 x2 x3 x4 y1y2y3y4 RAS FF11 RAS FF14 RAS FF12 RAS FF13 RAS FF11 RAS FF14 RAS FF12 RAS FF13 RAS FF21 RAS FF24 RAS FF22 RAS FF23 RAS FF31 RAS FF32 RAS FF33 RAS FF34 RAS FF41 RAS FF42 RAS FF43 RAS FF44 To Next Level RAS FF22 4-to-1 Scan-out Macrocell

12. 12 Scan-out Macrocell A 4x4 block scan-out data flow and control logic D-FFs may be inserted at the two outputs of macrocell for multi-cycle scan-out. To Next Level Output BUS Control Signal to Next Level BUS Data Bus From 4 RAS FFs { Control From 4 RAS FFs

13. 13 Routing of Decoder Signals in RAS COLUMN DECODER ROWDECODERROWDECODER Flip-Flops Placed on a Grid StructureAddress (log 2 √n ff ) (log 2 √ n ff ) Address

14. 14 Gate Area Overhead Gate area overhead of Serial Scan = Gate area overhead of Random Access Scan = where n ff – Number of Flip-Flops where n ff – Number of Flip-Flops n g – Number of Gates Assumption: D-FF contains 10 logic gates.

15. 15 Gate Area Overhead (Examples) 1. A circuit with 100,000 gates and 5,000 FFs Gate overhead of serial scan = 13.3 % Gate overhead of RAS = 20.0 % (Typical example from an industrial circuit. Details in later slide) 2. A circuit with 500,000 gates and 5,000 FFs Gate overhead of serial scan = 3.6 % Gate overhead of RAS = 5.5 %

16. 16 Overhead in Terms of Transistors Transistor overhead of Serial Scan = Transistor overhead of Random Access Scan = Where n t is number of transistors in comb. logic. D-flip-flop (28 transistors), serial scan FF (28+10) and RAS FF (28+26) were designed in 0.5μ CMOS technologyusing Mentor Graphics Design Architect. technology using Mentor Graphics Design Architect.

17. 17 Test Time

18. 18 Test Power

19. 19 Case Study on an Industrial Circuit A case study on an industry circuit was performed at Texas Instruments India Pvt. Ltd. The preliminary results were as follows: 1.The gate area overhead of RAS for a chip with ~5500 Flip-Flops and ~100,000 NAND equivalent gates was of the order of 18%. 2.4X reduction in test time was estimated. A speed- up of up to 10X was considered possible using ATPG heuristics. 3.Estimated routing and device area overhead of RAS in physical layout was 10.4%.

20. 20 Conclusion New design of a “Toggle” Flip-Flop reduces the RAS routing overhead. Proposed RAS architecture with new FF has several other advantages: –Algorithmic minimization reduces test cycles by 60%. –Power dissipation during test is reduced by 99%. A novel RAS scan-out method presented. For details on “Toggle” Flip-Flop, see Mudlapur et al., VDAT -05.