1. NCKU CSIE EDALAB Shang-Tsung Yu, Sheng-Han Yeh, and Tsung-Yi Ho jidung@eda.csie.ncku.edu.tw http://eda.csie.ncku.edu.tw Electronic Design Automation Laboratory Department of Computer Science and Information Engineering National Cheng Kung University Tainan, Taiwan ISPD 2014

2. NCKU CSIE EDALAB Outline 2 Introduction Problem Formulation Algorithm Experimental Results Conclusions

3. NCKU CSIE EDALAB Digital Microfluidic Biochips (DMFBs) ․ The architecture of DMFBs  2D microfluidic array: A set of basic cells for biological reactions  Droplets: Biological sample carrier as basic units to perform the laboratory procedures on a DMFB  Reservoirs/dispensing ports: Generate droplets  Optical detectors: Detection of reaction result 3

4. NCKU CSIE EDALAB Electrowetting-On-Dielectric Chips (EWOD Chips) ․ For EWOD chips, electrodes can be actuated by applying voltage to the electrode. 4 Side view Droplet Bottom plate Top plate Ground electrode Control electrodes Hydrophobic insulation Actuated Droplet Generated electrical field

5. NCKU CSIE EDALAB 5 Operation of Digital Microfluidics (1/3) Transport 25 cm/s flow rates, order of magnitude

6. NCKU CSIE EDALAB 6 Operation of Digital Microfluidics (2/3) Splitting/Merging

7. NCKU CSIE EDALAB 7 Droplet Dispensing Synchronization of many droplets Operation of Digital Microfluidics (3/3)

8. NCKU CSIE EDALAB Chip-Level Design of EWOD Chips ․ Bottom layer contains conduction wires, electrical pads, and a substrate ․ The routing problem: 2D pin array (routing inner electrodes to outside electrical pads) ․ How to control these electrodes 8 Bottom Layer

9. NCKU CSIE EDALAB Pin-Constrained EWOD chips ․ Huge number of electrodes in large-scale DMFBs ․ Limited number of ports in external controller ․ Broadcast addressing technique for pin-constrained - Reduce pin count and fabricate cost 9 Pin Count: 12 Pin Count: 5 Electrodes share the same control pin

10. NCKU CSIE EDALAB X Broadcast Electrode Addressing (1/2) ․ Electrode Actuation Sequence (AS)  An AS represents every status demanded at each time step 1: Actuated term 0: Grounded term X: Don’t care term ․ Share the same control pin  By observing, multiple electrodes can share an identical sequence by replacing X with 1 or 0 10 1X0100X 101XX11 1 00 1 Compatible time step123456 status of electrode10X01X These electrodes can be merged into the same control pin

11. NCKU CSIE EDALAB Broadcast Electrode Addressing (2/2) ․ Broadcast addressing constraint  If the actuation sequences are (aren’t) mutually compatible, they can (cannot) be addressed with the same control pin 11 e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e8e8 e9e9 e 10 e 11 e 12 Electrode groups : {e 1, e 2, e 9, e 10 }, {e 3, e 4, e 5, e 8, e 11, e 12 }, {e 6, e 7 } Pin 1 Pin 2 Pin 3 e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e8e8 e9e9 e 10 e 11 e 12 Compatibility graph Clique partition Electrode Compatible

12. NCKU CSIE EDALAB Reliability Issue (1/2) ․ Arbitrary broadcast addressing will cause huge number of switching times in resulting AS e1e1 e2e2 e3e3 10X0X0 1X0X00 X01X1X 101010 100000 10 e1e1 e2e2 e1e1 e3e3

13. NCKU CSIE EDALAB Reliability Issue (2/2) ․ Contact angle reduction problem [10]  High switching times will cause contact angle change reduction, and it will decrease the reliability especially in high frequency DMFB. 13 [10] L. Huang, B. Koo, and C. J. Kim, Evaluation of anodic Ta2O5 as the dielectric layer for EWOD devices," IEEE MEMS, pp. 428-431, 2012. Grounded Actuated

14. NCKU CSIE EDALAB Outline 14 Introduction Problem Formulation Algorithm Experimental Results Conclusions

15. NCKU CSIE EDALAB Problem Formulation 15

16. NCKU CSIE EDALAB Outline 16 Introduction Problem Formulation Algorithm Experimental Results Conclusions

17. NCKU CSIE EDALAB Algorithm 17 ․ The algorithm contains 2 main steps Step 1. Incremental search Step 2. Simultaneous broadcast addressing and routing

18. NCKU CSIE EDALAB Incremental Search Method (1/4) ․ Lower Bound of Switching Times (BST) 18 011100101 eliminate X terms

19. NCKU CSIE EDALAB Incremental Search Method (2/4) 19 e1e1 e2e2 e3e3 10X0X0 1X0X00 X01X1X 100000 (ST=1) S max = 3 S max = 5 101010 (ST=5)

20. NCKU CSIE EDALAB Incremental Search Method (3/4) 20 Simultaneous broadcast addressing and routing S max += 1 NO YES A feasible solution Feasible solution?

21. NCKU CSIE EDALAB Incremental Search Method (4/4) 21 high low ST infeasible feasible infeasible

22. NCKU CSIE EDALAB Simultaneous Broadcast Addressing and Routing (1/2) 22 Main idea: progressive solving Divide the original problem into a set of manageable sub-problems corresponding to a pin-electrode merging : Unaddressed electrodes : Addressed electrodes e8e8 e2e2 e3e3 e4e4 e6e6 e7e7 e1e1 e 10 e9e9 e5e5 e1e1 e2e2 e3e3 e4e4 e8e8 e7e7 e6e6 e5e5 e9e9 e5e5 e1e1 e8e8 e5e5 e8e8 e1e1 e2e2 e3e3 e6e6 e7e7 Set initial pins by a maximal independent set Broadcast addressing and routing e2e2 e3e3 e6e6 e7e7 e4e4 Set an unaddressed electrode as a new pin e4e4 Broadcast addressing and routing e9e9 e9e9 P2P2 P1P1 P3P3 P4P4 P5P5

23. NCKU CSIE EDALAB Simultaneous broadcast addressing and routing 23 Simultaneous broadcast addressing and routing S max += 1 NO YES A feasible solution Feasible solution? Identify an initial electrode set and address them with individual control pins Find pin-electrode candidates by network flow model NO 1. Trace the resulting flow 2. Routing check and conduct the broadcast addressing and routing Do escape routing and output the solution All electrodes are addressed? YES Simultaneous Broadcast Addressing and Routing (2/2)

24. NCKU CSIE EDALAB Network Flow Model (1/2) 24 Existed control pins Unaddressed electrodes ‧‧‧ P1P1 P2P2 P n-1 PnPn ST UE 1 UE 2 UE m-1 UE m Capacity = 1 Cost = 0 Capacity = 1 Cost = 0 Capacity = 1 Cost = HPWL-Extension( P i, UE j ) G scc

25. NCKU CSIE EDALAB Network Flow Model (2/2) ․ HPWL-Extension  The variation of half-perimeter wire length (The variation of half-perimeter of bounding box) 25 Cost = 3 Cost = 0 Using lower routing cost to do the broadcast addressing and routing

26. NCKU CSIE EDALAB Wire Routing ․ Pin-electrode merge  Only if there is a successful routing between a pin and an electrode, they can be merged 26 e1e1 e2e2 e8e8 routing check P1P1 Two-stage routing check will be conducted one by one from candidates candidate 1 candidate 2 candidate 3

27. NCKU CSIE EDALAB Wire Routing Check ․ Stage 1: Do wire routing check between existing pin and unaddressed electrode from candidates 27 Drop this pin-electrode merging!

28. NCKU CSIE EDALAB Escape Routing Check ․ Stage 2: Do escape routing check whenever a wire routing check (stage 1) is successful 28 Drop this pin-electrode merging! Escape routing Wire routing

29. NCKU CSIE EDALAB Conduct the Merging and Routing Successfully ․ If both the stage 1 and stage 2 checks are approved, conduct the merging and routing immediately 29 e1e1 e2e2 e8e8 routing check P1P1 e8e8 P1P1 e1e1 e2e2 candidate e8e8 conduct routing

30. NCKU CSIE EDALAB Matching Pairs in Order 30 P1P1 P2P2 P3P3 P4P4 ST UE 1 UE 2 UE 3 UE 4 UE 5 P5P5 7 9 12 5 20

31. NCKU CSIE EDALAB Blacklist of Failed Routing Pairs 31 P1P1 P2P2 P3P3 P4P4 ST UE 1 UE 2 UE 3 UE 4 UE 5 P5P5

32. NCKU CSIE EDALAB Review Algorithm Calculate Lower Bound of Switching Times Set Initial Switching-Constrained Construct Compatibility Graph Select an Initial Pin Set Resulting Flow = 0 ? NO Build MCMF Network Flow Model YES Routing Check, Merge Pins and Electrodes and Conduct Wire Routing Rebuild Compatibility Graph # of Unaddressed Electrodes = 0 ? YES Select an Unaddressed Electrode as a New Pin NO YES Meet Pin- Constrained ? End Switching-Constrained = Switching- Constrained + 1 NO Abandon Current Matching Results 29

33. NCKU CSIE EDALAB Outline 33 Introduction Problem Formulation Algorithm Experimental Results Conclusions

34. NCKU CSIE EDALAB Experimental Result (1/3) ․ Environmental Setup  CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz  Memory: 8GB DDR3-1600  Operating System: Linux Mint 15 Olivia with 64-bits  Programming Language: C++ ․ 5 real-life chips are used for test cases 34 ChipSize#EP max #Time StepBST amino6 X 820163412 Multiplex15 X 155932204 PCR15 X 156232206 Multifunctional15 X 1591647712 DNA preparation13 X 21773210612

35. NCKU CSIE EDALAB Experimental Result (2/3) 35 Chip BaselineOurs #PinGR(%)CPU#PinGR(%)CPU amino141316.67%0.1912140%0.15 multiplex1018150%29.64230%21.95 PCR1229100%33.26320%34.09 multifunctional165833.33%39.812610%37.62 DNA preparation222883.33%41.513318.33%70.78

36. NCKU CSIE EDALAB Experimental Result (3/3) 36

37. NCKU CSIE EDALAB Outline 37 Introduction Problem Formulation Algorithm Experimental Results Conclusions

38. NCKU CSIE EDALAB Conclusions ․ Reliability-driven chip-level design for high-frequency DMFB ․ A network flow based progressive addressing to handle the complex problem ․ The contact angle reduction problem is minimized. 38

39. NCKU CSIE EDALAB 39

40. NCKU CSIE EDALAB 40 Appendixes Appendixes Motivation for Microfluidic Biochips ․ Applications: Clinical diagnostics, environmental monitoring, automated drug discovery, etc. Test tubes Automation Integration Miniaturization Robotics Automation Integration Miniaturization nl-pl sample Microfluidics Biochips Automation Integration Miniaturization Higher throughput, minimal human intervention, smaller sample/reagent consumption

41. NCKU CSIE EDALAB Appendix Appendix Broadcast Electrode Addressing Droplet Spacing High voltage to generate an electrical field 0010XXX time X0010XX XX0010X XXX0010 XXXX001 Wire External controller Actuation sequence 00XXX00XXX 00XXX00XXX 1001010010 1001010010 0100101001 0100101001 7 pins -> 4 pins Broadcast addressing Electrode 41 impossible

42. NCKU CSIE EDALAB Appendixes Appendixes CAD Flow (1/2) 42 Sequencing Graph Microfluidic Module Library Design Spec. Architectural-Level Synthesis SchedulingResource Binding O1 O2 ResourceAreaTime Mixer2x2-array7 Mixer1x3-array4 LED1x1 cell10 Storage1x1 cellN/A O3 O4 O5 O6 Store Dispense Store Mix Detection OperationResource O1On-chip O22x2-array O31x1 cell O4LED O51x3-array O61x1 cell Max. Area: 5x5 array Max. Completion Time: 50 seconds O1O3O6 O5 O2 O4

43. NCKU CSIE EDALAB Appendixes Appendixes CAD Flow (2/2) 43 SchedulingResource Binding OperationResource O1On-chip O22x2-array O31x1 cell O4LED O51x3-array O61x1 cell Placement O2O1 O4O5 O6O3 Physical-Level Synthesis Routing O2O1 O4O5 O6O3 O1O3O6 O5 O2 O4