Presentation is loading. Please wait.

Presentation is loading. Please wait.

FPU structure. Assumptions (to shorten execution trace) – 2 instructions dispatched in order per cycle – execution begins in same cycle as dispatch –

Published byChandler Levers Modified over 9 years ago

Similar presentations

Presentation on theme: "FPU structure. Assumptions (to shorten execution trace) – 2 instructions dispatched in order per cycle – execution begins in same cycle as dispatch –"— Presentation transcript:

1 FPU structure

2 Assumptions (to shorten execution trace) – 2 instructions dispatched in order per cycle – execution begins in same cycle as dispatch – result broadcast on CDB in last cycle of execution Example Instruction sequence W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2 Initial register contents FLR tagdata F006 F202 F4010 F608

3 Cycle 1 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 14006 25202 34010 Ex unit 608 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 106084006 25202 34110 Ex unitW 608 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 106084061006 25242 34110 Ex unitW 608

4 Cycle 2 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 106084061006 25242 34110 Ex unitW 608 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 106084061006 21085242 34210 Ex unitW 608 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 106084061006 2108524242 34210 Ex unitW 658

5 Cycle 3 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 1406014006 20 08524242 34210 Ex unitY X658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

6 Cycle 4 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 1406014006 20 08524242 34210 Ex unitY X658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

7 Cycle 5 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 1406014006 250224242 340 Ex unit X658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

8 Cycle 6 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 14006 2502208420 34022 Ex unit Z658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

9 Cycle 7 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 14006 2502208420 34022 Ex unit Z658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

10 Cycle 8 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 14006 2502208420 34022 Ex unit Z658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

11 Cycle 9 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata 14006 252084 34022 Ex unit 601848 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

Download ppt "FPU structure. Assumptions (to shorten execution trace) – 2 instructions dispatched in order per cycle – execution begins in same cycle as dispatch –"

Similar presentations

The Fetch – Execute Cycle

The Fetch – Execute Cycle
Memory. Memory.

Memory. Memory.
Machine cycle.

Machine cycle.
Module Invocation & Parameters Tracing the Execution of Instructions with the Activation Stack.

Module Invocation & Parameters Tracing the Execution of Instructions with the Activation Stack.
The Build-up of the Red Sequence at z

The Build-up of the Red Sequence at z
Simple Graph Warmup. Cycles in Simple Graphs A cycle in a simple graph is a sequence of vertices v 0, …, v n for some n>0, where v 0, ….v n-1 are distinct,

Simple Graph Warmup. Cycles in Simple Graphs A cycle in a simple graph is a sequence of vertices v 0, …, v n for some n>0, where v 0, ….v n-1 are distinct,
Assumptions One instruction can be fetched at each cycle. Latency is 2 cycles for ALU, and 3 for multiplier Instructions begin execution once fetched In.

Assumptions One instruction can be fetched at each cycle. Latency is 2 cycles for ALU, and 3 for multiplier Instructions begin execution once fetched In.
INSTRUCTION-LEVEL PARALLEL PROCESSORS

INSTRUCTION-LEVEL PARALLEL PROCESSORS
Central Processing Unit

Central Processing Unit
1 ECE369 ECE369 Pipelining. 2 ECE369 “toupper” :converts any lowercase characters (with ASCII codes between 97 and 122) in the null-terminated argument.

1 ECE369 ECE369 Pipelining. 2 ECE369 “toupper” :converts any lowercase characters (with ASCII codes between 97 and 122) in the null-terminated argument.
CS364 CH16 Control Unit Operation

CS364 CH16 Control Unit Operation
RISC and Pipelining Prof. Sin-Min Lee Department of Computer Science.

RISC and Pipelining Prof. Sin-Min Lee Department of Computer Science.
Instruction Level Parallelism María Jesús Garzarán University of Illinois at Urbana-Champaign.

Instruction Level Parallelism María Jesús Garzarán University of Illinois at Urbana-Champaign.
COMP25212 Advanced Pipelining Out of Order Processors.

COMP25212 Advanced Pipelining Out of Order Processors.
Damian BrowneLuis PabonPedro Tovar The operation of a computer in executing a program consists of a sequence of Instruction Cycles, with one machine.

Damian BrowneLuis PabonPedro Tovar The operation of a computer in executing a program consists of a sequence of Instruction Cycles, with one machine.
6/9/2015TUC-N dr. Emil CEBUC Math Coprocessor Also called Floating Point Unit FPU.

6/9/2015TUC-N dr. Emil CEBUC Math Coprocessor Also called Floating Point Unit FPU.
7/14/2000 Page 1 Design of the IRAM FPU Ioannis Mavroidis IRAM retreat July 12-14, 2000.

7/14/2000 Page 1 Design of the IRAM FPU Ioannis Mavroidis IRAM retreat July 12-14, 2000.
The AMD K8 Processor Architecture December 14 th 2006.

The AMD K8 Processor Architecture December 14 th 2006.
1 Zvika Guz Slides modified from Prof. Dave Patterson, Prof. John Kubiatowicz, and Prof. Nancy Warter-Perez Out Of Order Execution.

1 Zvika Guz Slides modified from Prof. Dave Patterson, Prof. John Kubiatowicz, and Prof. Nancy Warter-Perez Out Of Order Execution.
CSCE 212 Quiz 4 – 2/16/11 *Assume computes take 1 clock cycle, loads and stores take 10 cycles and branches take 4 cycles and that they are running on.

CSCE 212 Quiz 4 – 2/16/11 *Assume computes take 1 clock cycle, loads and stores take 10 cycles and branches take 4 cycles and that they are running on.

Similar presentations

Ads by Google