1. 1 CS 140L Lecture 8 System Design Professor CK Cheng CSE Dept. UC San Diego

2. 2 Lab4. System Design Inst(Data) R1 R2 R3 Output Data Path Control Subsystem

3. 3 Three instruction bits and 4 data bits. I2I2 I1I1 I0I0 D3D3 D2D2 D1D1 D0D0 idI2I1I0Op 0000Init 1001Move 1 2010Move 2 3011Store 4100Add 5101Shift 6110Comp 7111Mask Instruction Set

4. 4 Init: R1 = R2 = R3 = (0,0,0,0) Initialize all three registers to 0 Mov1: R1 = (D 3, D 2, D 1, D 0 ) Move data D3-0 to R1 Mov2: R2 = (D 3, D 2, D 1, D 0 ) Move data D3-0 to R2 Store: R2 <= R3 Store data into R2 from R3 Add: R3 <= R1 + R2, Overflow flag Add R1 and R2 and store the sum in R3 Shift: R3 <= (R2 Shift left by (D 3, D 2 ) bits) Shift R2 by D3-2 bits and store the result in R3 Comp: flag(R1, R2) R2 Compare R1 and R2 and set flag=1 if R1 is bigger And: R3 <= (R1)&(R2) AND bitwise R1 and R2. Store the result in R3 Instruction Set

5. 5 Overview of System Design D0D0 D1D1 D2D2 D3D3 I0I0 I1I1 I2I2 Data Input D 3-0 Control Input I 2-0, D 3-2 Control Signals Conditions Data output Control output Data Subsystem Control Subsystem

6. 6 Data Path Subsystem

7. 7 Control Subsystem Control Subsystem D2D2 D3D3 I0I0 I1I1 I2I2 CLR En1 En2 En3 S0S0 S1S1 S2S2 S3S3 S4S4 S5S5

8. 8 Control Subsystem I2-0ClrEn 1-3 S2S1S2S1 S0S0 S5S5 S4S3S4S3 CLR0001------- Move10010100---- Move20100 --0- Store0110010--1- +100000100-0-- <<101000101--D3D2D3D2 Comp1100000---1 &111000111---- 8 Data R2 D 3-0 0101 S0S0 En2 CLR R1 CLR + << Comp & 0101 S5S5 Flag S4S4 S3S3 En1 01230123 R3 En3 CLR S2S2 S1S1 clk overflow clk