1. Digital Integrated Circuits A Design Perspective
EE141
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
Timing Issues
January 2003

2. Synchronous Timing

3. Timing Definitions

4. Latch Parameters D Q Clk T Clk PWm tsu D thold tc-q td-q Q
Delays can be different for rising and falling data transitions

5. Register Parameters D Q Clk T Clk thold D tsu tc-q Q
Delays can be different for rising and falling data transitions

6. Clock Uncertainties
Sources of clock uncertainty

7. Clock Nonidealities Clock skew Clock jitter
Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
Clock jitter
Temporal variations in consecutive edges of the clock signal; modulation + random noise
Cycle-to-cycle (short-term) tJS
Long term tJL
Variation of the pulse width
Important for level sensitive clocking

8. Clock Skew and Jitter
Clk
tSK
Clk
tJS
Both skew and jitter affect the effective cycle time
Only skew affects the race margin

9. Clock Skew # of registers Earliest occurrence of Clk edge
Nominal – /2
Latest occurrence of Clk edge
Nominal +  /2
Clk delay
Insertion delay
Max Clk skew 

10. Positive and Negative Skew

11. Positive Skew
Launching edge arrives before the receiving edge

12. Negative Skew
Receiving edge arrives before the launching edge

13. Timing Constraints Minimum cycle time: T -  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

14. Timing Constraints Hold time constraint:
t(c-q, cd) + t(logic, cd) > thold + 
Worst case is when receiving edge arrives late Race between data and clock

15. Impact of Jitter

16. Longest Logic Path in Edge-Triggered Systems
TJI + d
TSU
Clk
TClk-Q
TLM T
Latest point of launching
Earliest arrival of next cycle

17. Clock Constraints in Edge-Triggered Systems
If launching edge is late and receiving edge is early, the data will not be too late if:
Tc-q + TLM + TSU < T – TJI,1 – TJI,2 - d
Minimum cycle time is determined by the maximum delays through the logic
Tc-q + TLM + TSU + d + 2 TJI < T
Skew can be either positive or negative

18. Shortest Path Clk TClk-Q TLm Clk TH Earliest point of launching
Data must not arrive before this time
Nominal clock edge

19. Clock Constraints in Edge-Triggered Systems
If launching edge is early and receiving edge is late:
Tc-q + TLM – TJI,1 < TH + TJI,2 + d
Minimum logic delay
Tc-q + TLM < TH + 2TJI+ d

20. How to counter Clock Skew?

21. Flip-Flop – Based Timing
Skew
Flip-flop delay
Logic delay f
TSU
TClk-Q
Flip -flop
f = 1
f = 0
Logic
Representation after M. Horowitz, VLSI Circuits 1996.

22. Flip-Flops and Dynamic Logic
Logic delay
TSU
TSU
TClk-Q
TClk-Q
f = 1
f = 1
f = 0
f = 0
Logic delay
Precharge
Precharge
Evaluate
Evaluate
Flip-flops are used only with static logic

23. Latch timing tD-Q When data arrives to transparent latch
Latch is a ‘soft’ barrier D Q
Clk
tClk-Q
When data arrives
to closed latch
Data has to be ‘re-launched’

24. Single-Phase Clock with Latchesf
Latch
Logic
Tskl
Tskl
Tskt
Tskt
Clk PW P

25. Latch-Based Design L1 latch is transparent when f = 0
Logic
Latch
Latch
Logic

26. Slack-borrowing

27. Latch-Based Timing f = 1 f = 0 Can tolerate skew! Skew Static logic
L2 latch
f = 1 L1 L2
Logic
Latch
Latch
L1 latch
Logic
f = 0
Long
path
Can tolerate skew!
Short
path

28. Clock Distribution
H-tree
Clock is distributed in a tree-like fashion

29. More realistic H-tree
[Restle98]

30. The Grid System
No rc-matching
Large power

31. Example: DEC Alpha 21164

32. 21164 Clocking Clock waveform Location of clock driver on die
EE141
21164 Clocking
tcycle= 3.3ns
2 phase single wire clock, distributed globally
2 distributed driver channels
Reduced RC delay/skew
Improved thermal distribution
3.75nF clock load
58 cm final driver width
Local inverters for latching
Conditional clocks in caches to reduce power
More complex race checking
Device variation
trise = 0.35ns
tskew = 150ps
Clock waveform
pre-driver
final drivers
Location of clock
driver on die

34. Clock Skew in Alpha Processor

35. EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS trise = 0.35ns
EE141
EV6 (Alpha 21264) Clocking
600 MHz – 0.35 micron CMOS
trise = 0.35ns
tskew = 50ps
tcycle= 1.67ns
Global clock waveform
2 Phase, with multiple conditional buffered clocks
2.8 nF clock load
40 cm final driver width
Local clocks can be gated “off” to save power
Reduced load/skew
Reduced thermal issues
Multiple clocks complicate race checking

36. 21264 Clocking

37. (20% to 80% Extrapolated to 0% to 100%)
EE141
EV6 Clock Results ps
300
305
310
315
320
325
330
335
340
345 ps 5 10 15 20 25 30 35 40 45 50
GCLK Skew
(at Vdd/2 Crossings)
GCLK Rise Times
(20% to 80% Extrapolated to 0% to 100%)

38. EV7 Clock Hierarchy Active Skew Management and Multiple Clock Domains
EE141
EV7 Clock Hierarchy
Active Skew Management and Multiple Clock Domains
+ widely dispersed drivers
+ DLLs compensate static and low- frequency variation
+ divides design and verification effort
- DLL design and verification is added work
+ tailored clocks

39. Self-timed and Asynchronous Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
1) Completion is ensured by careful timing analysis
2) Ordering of events is implicit in logic
Self-timed design
1) Completion ensured by completion signal
2) Ordering imposed by handshaking protocol

40. Synchronous Pipelined Datapath

41. Self-Timed Pipelined Datapath

42. Completion Signal Generation

43. Completion Signal Generation

44. Completion Signal in DCVSLDD DD B
Start
Done B 1 B B 1 In 1 In 1
PDN
PDN In 2 In 2
Start

45. Self-Timed Adder

46. Completion Signal Using Current Sensing

47. Hand-Shaking Protocol
Two Phase Handshake

48. Event Logic – The Muller-C Element

49. 2-Phase Handshake Protocol
Advantage : FAST - minimal # of signaling events (important for global interconnect)
Disadvantage : edge - sensitive, has state

50. Example: Self-timed FIFO
All 1s or 0s -> pipeline empty
Alternating 1s and 0s -> pipeline full

51. 2-Phase Protocol

52. Example
From [Horowitz]

53. Example

54. Example

55. Example

56. 4-Phase Handshake Protocol
Also known as RTZ
Slower, but unambiguous

57. 4-Phase Handshake Protocol
Implementation using Muller-C elements

58. Self-Resetting Logic
Post-charge logic

59. Clock-Delayed Domino

60. Asynchronous-Synchronous Interface

61. Synchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events occurred first
Synchronizer: Arbiter with clock f as one of the inputs
Problem: Circuit HAS to make a decision in limited time - which decision is not important
Caveat: It is impossible to ensure correct operation
But, we can decrease the error probability at the expense of delay

62. A Simple Synchronizer • Data sampled on rising edge of the clock
• Latch will eventually resolve the signal value,
but ... this might take infinite time!

63. Synchronizer: Output Trajectories
Single-pole model for a flip-flop

64. Mean Time to Failure

65. Example

66. Influence of Noise
Low amplitude noise does not influence synchronization behavior

67. Typical Synchronizers
2 phase clocking circuit
Using delay line

68. Cascaded Synchronizers Reduce MTF

69. Arbiters

70. PLL-Based Synchronization

71. PLL Block Diagram

72. Phase Detector
Output before filtering
Transfer characteristic

73. Phase-Frequency Detector

74. PFD Response to Frequency

75. PFD Phase Transfer Characteristic

76. Charge Pump

77. PLL Simulation

78. Clock Generation using DLLs
Delay-Locked Loop (Delay Line Based)
fREF U
Phase Det
Charge Pump DL D
Filter fO
Phase-Locked Loop (VCO-Based)
fREF U PD CP
VCO D ÷N
Filter fO

79. Delay Locked Loop

80. DLL-Based Clock Distribution