1. Chapter 3 Addressing Modes
DSP C5000
Chapter 3
Addressing Modes
Copyright © 2003 Texas Instruments. All rights reserved.

2. Objectives
Present the main addressing modes and allocation of sections
Present the main addressing modes of the C54 family
Present the main addressing modes of the C55 family
Explain how to use these addressing modes
Do exercises to practice using the different addressing modes

3. Generalities on addressing modes
Outline
Generalities on addressing modes
C54x
C55x

4. Addressing Modes: What are the Problems?
Specify operands per instruction:
A single instruction can access several operands at a time thanks to the many internal data busses,
But how do we specify many addresses using a small number of bits?
Repeated processing on an array of data:
Many DSP operations are repeated on an array of data stored at contiguous addresses in data memory.
There are cases where it is useful to be able to modify the addresses as part of the instruction (increment or decrement).
Instruction size and PIPELINE :
The code of the instruction must remain short in order not to break the pipeline.

5. Main Addressing Modes of C5000 Family
Immediate addressing
Absolute addressing
Direct addressing
Indirect addressing by register
Support for circular indirect addressing
Definition
Access to Memory Mapped Registers MMRs
Immediate addressing
The instruction contains the value of the operand.
Absolute addressing
The instruction contains the complete address of the operand.
Direct addressing
The instruction contains a part of or an offset to the address of the operand relative to a base address.
Indirect addressing
The address of the operands are stored in specific registers. Uses registers as pointers

6. Allocating Sections

7. Example System Diagram Algorithm y = x1 + x0 + x2 Procedure
C5000 CPU
System Diagram
DROM
init[3]
EPROM
(code)
y = x1 + x0 + x2
Algorithm
Allocate sections (code, constants, vars)
Setup addressing modes
Add the values (x1 + x0 + x2)
Store the result (y)
Procedure
We consider a simple example:
We want to calculate the sum of 3variables x0+x1+x2.
The result is y.
The system contains:
an external memory where we identify 2 different blocks named: DROM and EPROM. In DROM we will store the constants (Data Rom)
In EPROM we will store the program.
An internal memory where we will store the values of the variables x and y during calculation.
The programmer should write relocatable code. He should not have to give the exact address where to read
The code in program memory or where to read the data in data memory.
The assembler and the linker allow to use symbolic addresses and work with coff files:
COFF = Common Object File Format.
How do we allocate the proper sections?

8. Writing relocatable code
The programmer should not have to give the exact addresses:
where to read the code in program memory,
where to read the data in data memory.
The assembler allows to use symbolic addresses.
The assembler and the linker work with COFF files:
COFF = Common Object File Format.
In COFF files, specialized sections are used for code, variables or constants.
The programmer specifies in a command file for the linker where the different sections should be allocated in the memory of the system.
The programmer should write relocatable code.
In coff files, different kinds of sections are used to store code, variables or constants.

9. Definition of Sections
Different sections for code, vars, constants.
The sections can be initialized or not.
An initialized section is filled with code or constant values.
An uninitialized section reserves memory space for a variable.
The sections can have default names or names given by the programmer.

10. Definition and names of Sections
The programmer uses special directives to identify the sections.
A directive is a command that is given to the asembler. It always begin with a dot: .bss for example.
The directives .text, .data, .sect, .usect, .bss identifies the type of sections.
For example, after the directive .text, the programmer writes a part of code.
With the directive .bss, the programmer reserves memory space for uninitialized data.
The programmer can give a specific name to a section.
For example the directive:
.sect ‘’my_name ’’
Identifies an initialized section with the name my_name.

11. How are these sections placed into the memory areas shown?
Example of sections
Initialized named section: Initialization of constants. Definition of address tbl
Uninitialized named section: x[3], y[1], Definition of address x and y.
Initialized named section: code
System Diagram
DROM
tbl[3]
How are these sections placed into the memory areas shown?
RAM
x[3]
Visual Linker (or the command file of the linker) will place the sections (x, y, tbl, code) into the “Not Yet Placed” folders - code, constants, variables. The user then drags the sections into the memory areas shown on the system diagram.
The section ‘’init’’ contains the initialized table beginning at the address tbl. It should be allocated to the DROM memory in the example system.
The uninitialized, named section ‘’vars’’, beginning at address x, should be allocated to the physical RAM internal memory.
This section has a length of 3 words .
The uninitialized, named section ‘’result’’, beginning at address y, should be allocated to the physical RAM internal memory.
This section has a length of 1 word.
The initialized and named section ‘’code’’ that will contain the code should be allocated in the external memory EPROM of the system.
EPROM
code
RAM y
54x CPU

12. C54x Addressing Modes

13. Format of Data and Instructions, Internal Busses of the C54x Family
In the C54x DSP, the data and program memories are organized in 16-bit words. Data busses have a 16-bit width.
Data and instructions are generally of size N=16 bits.
Some instructions may take several 16-bit words.
Some data operands may be double precision and occupy 2 words.
Internal busses: 2 data read, 1 data write
In the C54x

14. Terms from the User’s Guide

15. Immediate Addressing Mode #
Instruction contains the value of the operand. Value is preceded by #.
Example:
Add the value 4 to the content of accumulator A.
Useful for initializations.
Long (16 bits) or short values:
For long values: instruction uses 2 words.
ADD #4,A

16. Immediate Addressing Mode #
16 bit value
2 words, 2 cycles
Initialization of ARi for example
Short value
3, 5, 8, 9 bits constant
1 word, 1 cycle
To initialize short length registers or bit fields:
DP, ASM …
Not always available
Example:
STM #1234h,AR2
Load AR2 with the value 1234h.
Example:
LD #6, DP
Load DP with the value 6.
Here DP refers to the Data Page Register.
ASM is a bit field (5 bits) in the status word ST1 that specifies in certain instructions the number of shifts to be done on an accumulator.

17. Example: MMR (Memory Mapped Registers) and Immediate Addressing
STM (STore to Memory-mapped register) stores an immediate value to the specified MMR or Scratch address.
#tbl is the 16-bit address of the first element of the array tbl.
MMR = Memory Mapped Registers
Scratch memory

18. Direct Addressing Mode @
Direct addressing = random access from a specified base address.
The instruction contains an offset relative to the base address.
The base address can be the beginning of a data memory page or the stack pointer.
The data memory is virtually divided in 512 pages of 128 words (512x128 = 216).
Data Page DP relative direct address
CPL bit (ComPiler Mode bit) = 0 in ST1
Stack Pointer SP relative direct address
CPL bit = 1 in ST1
Here ST1 is Status Register 1.
In Direct addressing mode : The instruction contains a part of or an offset to the address of the operand.
The programmer must configure the CPL bit to choose what kind of direct addressing mode he wants to use.
He must also initialize the DP register in the case of a DP Relative addressing mode.

19. Data memory pages

20. Direct Addressing Mode @
For DP relative mode:
The 16 bit address is split into 9 MSB and 7 LSB.
The 7 LSB of the operand address are given in the instruction,
The 9 MSB are in the DP register.
For SP relative mode
The 7 bits given in the instruction are used as an offset from the SP to obtain the address.
In both cases, only 7 bits are used in the instruction for the operand address.

21. Direct Addressing Mode @
DP relative, CPL = 0
Opcode
I=0
dma
15 - 8 7
6 - 0
Instruction
DP register
9-bit DP
Address
9-bit DP
7-bit dma
SP relative, CPL = 1
SP Register
16-bit Stack Pointer
Dma = data memory address (7 bits offset relative to the base address) +
7-bit dma
Address
16-bit Data Memory Address

22. Direct Addressing Mode @, example
DP = 2, page 2
Offset in the instruction = 1
Address = 0101 in hexadecimal

23. Example
This instruction loads the upper 9 bits of address x into DP (in ST0)
Concept of Blocking:
Blocking is used to force the linker to put data to be same page.
It can be specified in the assembler file or in the linker command file.
The concept of Blocking is further described in the next slide.
CPL = 0
To be sure that x and x+1 are in the same page: use Blocking.

24. Direct Addressing Mode @, DP relative
When DP is initialized, it allows single-word single-cycle instructions with easy to understand symbols for addresses.
Defines 512 pages (selected by the 9 bits of DP) of 128 words (selected by the 7 bits in instruction) in data memory.
CPL is reset by:
RSBX CPL ; CPL = 0 on reset
Blocking of data in the same page
In the linker command file:
.bss : > RAM BLOCK = 128
In the assembler file
.bss x, 2, 1 ; specify all variables in one page
Here CPL refers to compiler mode.

25. Direct Addressing Mode @, SP relative
Used by the C compiler
Useful for stack based operations
Controlled by the CPL bit. Set by:
SSBX CPL

26. Indirect Addressing Mode *ARi
Compatible with pointers in C.
8 ARi Auxiliary Registers to store the addresses of the operands. They are used as pointers.
2 ARAU = Auxiliary Registers Arithmetic Units to realize operations on the addresses stored in the ARi.
1 operand (Smem) or 2 operands (Xmem, Ymem) can be specified by indirect addressing in 1 instruction.
Very efficient for DSP operations.
The addresses of the operands are stored in specific registers. Uses registers as pointers.
Certain instructions do not support direct addressing, so in these cases indirect addressing must be used.

27. Indirect addressing mode *ARi
AR0 can be used as an index.
Support for circular addressing
details in next slides
Bit Reversed BR addressing for FFT
ARi can be modified during the instruction
The possible modifications or operations on ARi depend on the number of operands specified by indirect addressing in the instruction.
Pointers (ARi) must be initialized before use.
Details on Bit Reverse addressing can be found in chapter 19.

28. Circular buffer and addressing on C54x

29. Circular addressing with C54x
Circular indirect addressing mode: %
*ARi-%, *ARi+%, *ARi-0%, *ARi+0%, *ARi(lk)%
In dual operand mode Xmem, Ymem:
*ARi+0% only valid mode
To perform a decrement, store a negative value in AR0.
BK register:
Stores the size N of the circular buffer.
Must be initialized before use.
There may be several circular buffers at different addresses at the same time but with the same length.

30. Limitations on Start Addresses of Circular Buffers
If N is written on nb bits in binary, the start address must have its nb LSB at 0:
Examples:
for N=32, 6 LSB of start address =0
for N=30, 5 LSB of start address =0
To access a circular buffer:
Initialize BK with N (nb bits)
Choose 1 ARi as a pointer
The effective start address of the buffer is the value in ARi with its nb LSB at 0.
The end address = start addess +N-1.

31. Indirect Addressing: ARi Specifications and Options for Modification
For a single operand Smem:
16 possible options for Smem,
4 bits for the option + 3 bits for the ARi.
The address is specified by = 7 bits.
For 2 operands Xmem, Ymem:
Only 4 ARi can be used: AR2 to AR5.
Only 4 possible options for the operations on the ARi.
Each address needs = 4 bits, so 2x4=8 bits are necessary for the 2 addresses.

32. Indirect Addressing Options for ARi modifications, Single operand Smem

33. Indirect Addressing Options for ARi for Double Operand Xmem and Ymem

34. Indirect Addressing Mode *ARi
There are latencies to consider:
no latency STM, MVDK
1 cycle MVDM, MVKD, MVDD
2 cycles STLM, ST, etc
ARi are read/modified in access phase, so the debugger will appear to show ARs changing early.
CMPT must = 0 (bit5, ST1)
is 0 on reset
is forced to 0 with RSBX CMPT
CMPT (Compatibility Mode Bit) = 1 allows ‘C2x/’C2xx/C5x styled ARP operation for ARs. But this mode is discouraged.
Here the word latency means that because of the pipeline, a certain amount of time must elapse before the registers can be used again.
The C54x has an improved architecture compared to the ‘C2x, ‘C2xx and ‘C5x. In practice, using CMPT = 1 is not taking advantage of the C54x architecture.

35. Example System Diagram Initialization of AR1 and AR2.
Copy the values from table in DROM to RAM (via A). Indirect addressing allows sequential access to data.
System Diagram
DROM
tbl[3]
RAM
x[3]
EPROM
code
RAM y
54x CPU

36. Absolute Addressing Mode *()
Allows us to specify a complete operand address in an instruction. *(Address)
The address can be in data, program or IO memory. 16 bits.
2 words, 2 cycles.
Data Memory
Addr
Data
x: 01FF 1000 y:
.data
x: .word 1000h
y: .word 0500h
.text
LD *(x),A
Acc A
ADD *(y),A

37. Example System Diagram DROM tbl[3] RAM x[3] EPROM code RAM y 54x CPU
Save accumulator A at address y

38. MMR Memory Mapped Registers Addressing
MMRs are in page 0 of data memory.
They can be accessed by some specific MMR instructions allowing simple access to page 0.
In these cases DP, SP and CPL are ignored
LDM, STLM MMR « Acc
STM # ® MMR
PSHM, POPM MMR « Stack
MVDM, MVMD MMR « Dmem
MVMM AR, SP « AR, SP
0000h
0060h
007Fh
MMRs
Scratch
Tip: use the .mmregs directive to allow MMR names to be interpreted as addresses

39. MMR Memory Mapped Registers
Addr. Name (Hex) Description
IMR 0000 Interrupt Mask Register
IFR 0001 Interrupt Flag Register
Reserved
ST Status 0 Register
ST Status 1 Register
AL 0008 A accumulator low (A[15:00])
AH 0009 A accumulator high (A[31:16])
AG 000A A accumulator guard (A[39:32])
BL 000B B accumulator low (B[15:00])
BH 000C B accumulator high (B[31:16])
BG 000D B accumulator guard (B[39:32])
T 000E Temporary Register
TRN 000F Transition Register
Addr. Name (Hex) Description
AR Address Register 0
AR Address Register 1
AR Address Register 2
AR Address Register 3
AR Address Register 4
AR Address Register 5
AR Address Register 6
AR Address Register 7
SP 0018 Stack Pointer Register
BK 0019 Circular Size Register
BRC 001A Block Repeat Counter
RSA 001B Block Repeat Start Address
REA 001C Block Repeat End Address
PMST 001D PMST Register
E-01F Reserved
Note: XPC and Peripheral MMR locations are device dependent

40. MMR Memory Mapped Registers Addressing
When accessing MMRs, latencies need to be considered.
STM (STore to Memory-mapped register):
Stores an immediate value to the specified MMR or Scratch memory address.
Writes the values during the access phase of the pipeline to avoid latencies.
The scratch memory is a RAM memory located in the page 0 of the data memory contiguous at addresses from 60 to 7F in hexadecimal.
The MMR registers addresses are from 0 to 5F.

41. Exercise on Addressing Modes of C54x
Given: DP=0 DP=4 DP=6
Address/Data (HEX)
CPL=
CMPT=
120
260
390
380
Addr Mode
Program A B DP AR0 AR1 AR2
LD #0,DP
STM #2,AR0
STM #200h,AR1
STM #300h,AR2
ADD *AR1+,A
ADD *AR1+,B,A
LD #6,DP
ADD *AR2+,A
SUB *AR2+,A
SUB #32,A
ADD *AR1-0,A,B
SUB *AR2-0,B,A
STL A,62h

42. Exercise on Addressing Modes of C54x
Given: DP=0 DP=4 DP=6
Address/Data (HEX)
CPL=
CMPT=

43. C55x Addressing Modes

44. Format of Data and Instructions, Internal Busses for the C55x Family
Unified program-data memory map: byte-aligned for program and word-aligned for data.
Has a variable length instruction set ( bits).
Program address bus: 24 bits, 16 Mbytes
4 instructions bytes are fetched at a time
6 bytes are decoded at a time
Internal data busses: 3 data read, 2 data write
Data addresses: 8 Mwords of 16 bits segmented into 64K pages, 23-bit address. A 24-bit address is automatically generated by the hardware by adding a LSB = 0.

45. C55x Addressing Modes Direct Indirect Absolute MMR
Loading constants in registers (e.g. immediate)
y = x0 + x1 + x2
Algorithm
RAM
x[3] y I P D A
55xx CPU
System Diagram
ROM
tbl[3]
y = x0 + x x2
This algorithm will again be used as an example for the different addressing modes.

46. Loading Constants in Registers #
Used for initialization of registers.
Used to be called immediate addressing
Addressing registers:
16-bits long: ARi, DP, CDP (Coefficient Data Pointer)
23-bits long: XARi, XDP, XCDP
The 7 MSB of Xreg specify the 64K page.
The ARAU auxiliary Register Arithmetic Unit is 16 bits wide: update of ARi and CDP are done modulo 64K.
Initialization example:
AMOV #adr,XAR3

47. Example = x .usect “vars”,4 y .usect “vars”,1 .sect “init”
tbl .int 1,2,3,4
.sect “code”
16-bit ARn
23-bit XARn X
indir: AMOV #x,XAR0
AMOV #tbl,XAR6 =
23-bit address
RAM
x[3] y I P D A
55xx CPU
ROM
tbl[3]
y = x0 + x x2

48. Direct Addressing Mode @
Gives the instruction a positive 7bit offset from DP (non-aligned).
In the case where the bit CPL=0 in ST1.
Calculation in the ARAU modulo 64K
23-bit XDP X
16-bit DP + =
23-bit address
This is different from the C54x DP Related direct addressing mode.
In the C54x the 7 bits given in the instruction specifies an address into a page of 128 words.
The beginning address of the pages are aligned on multiples of 128.
For the C55x, the 7 bits specifies an offset relative the the 16 bits DP register.

49. Example How is XDP initialized? x .usect “vars”,4 y .usect “vars”,1
.sect “init”
tbl .int 1,2,3,4
.sect “code”
RAM
x[3] y I P D A
55xx CPU
ROM
tbl[3]
y = x0 + x x2
ADD: MOV @(x+0),AC0
ADD @(x+1),AC0
ADD @(x+2),AC0
How is XDP initialized?

50. Example A in AMOV means in AD-phase.
The MDP has to be reloaded every time we cross a 64K page.
Constant value contained in instruction opcode
(-x) used in instruction to tell the assembler HOW to create the 7-bit offset from non-aligned XDP

51. Directive .dp for Direct Addressing
Instead of using (-x) to help the assembler calculate the proper 7-bit offset,
We can use the directive .dp to set the base address for the assembler calculation of the 7-bit offset.
.dp base_address
in the instruction is interpreted as a 23-bit address.
The .dp provides a compile-time base address.
The assembler determines the 7-bit offset by:

52. Indirect Addressing Mode *ARi
Similar to the case of the C54x, but:
23-bit addresses,
Extended registers XARi on 23 bits specify the complete address,
ARAU calculates on 16 bits (modulo 64K),
8 ARi 16-bit pointers used in the instructions.

53. Indirect Addressing Options for Pointer ARi Modifications
The ARi registers can be modified by offset stored in registers T0 or T1: *ARn(T0/1) or by a constant: *ARn(#k16).
#K16 is a signed 15-bit offset, so it can be + or - 32K as long as the main data page boundary is respected.
Please note that the following syntaxes will NOT work properly if the reset condition of C54CM=1 is left unchanged:
*(ARn +/- T0), *ARn(T0).
If C54CM =1, AR0 will be used in place of T0. If C54CM=0, these instructions will work properly.
The values used in T0/T1 and #k16 are 15-bit SIGNED integers. You can use a positive OR negative value.
Assumes ST2_55ARMS=0 and ST1_55C54CM=0.
The reset condition is C54CM=1.

54. Address Register Mode Select Bit ARMS
ARMS bit = bit 15 of ST2_55
ARMS=0 at reset DSP mode
For ARMS=1, CONTROL mode
T1 cannot be used as offset
No bit reversed addressing
New mode:
*ARi(short(#k3)) or *SP(short(#k3))
Useful for the C compiler
The C compiler sets ARMS = 1.
T1 is one of the 4 temporary registers T0, T1, T2, T3.
TA can be used as an offset for the Auxiliary registers ARn.

55. Modifying TAs Registers
TAx registers = T0-3, AR0-7.
Special instructions:
AADD, ASUB, AMOV
Can be used to modify TAs registers during the address (AD) phase of the pipeline, while instructions without A operates during the execution (X) phase.
They only work on the TAx registers.
The TA registers are the Temporary + the Auxiliary registers.
Examples:

56. Example
RAM
x[4] y I P D A
55xx CPU
ROM
tbl[4]
y = x0 + x x1

57. Circular Buffer Addressing Mode

58. Circular Buffer Addressing Mode
The even XARn (i.e. 0,2,4,6) determines the 64K Page

59. Selecting Circular or Linear Addressing Mode
Use the LSB of Status word ST2_55
Set or reset status bits:
If BK=0 or BK=FFFF, linear = circular.

60. Circular Buffer Exercise
Use AR4 as a circular pointer to x{5}:
Results are cumulative

61. Comparison of C54x and C55x circular addressing modes
3 BK registers in C55X instead of 1 in C54x: allows for several simultaneous circular buffers with different size.
In C54x, circular addressing mode is specified in indirect addressing type % in the instructions.
In C55x, the mode in set in status register ST2_55 for each register (linear or circular). No memory alignment constraint.

62. Absolute Addressing *(#)
*(#) = 23 bit address
Fast: no initialization,
But long instruction because it contains the 23 bit address.
If the address is in the 64K work page, it is possible to specify a 16-bit only address:
abs16*(#label)

63. Example
RAM
x[4] y I P D A
55xx CPU
ROM
tbl[4]
y = x0 + x x2

64. MMR Addressing Using mmap()
MMRs are located between 0 and 5F.
Scratch memory is located between 60 and 7F.
mmap() forces bits 22:7 to zero.
Useful to access MMR and scratch memory without initialization of addressing registers.
Useful only for direct addressing.
The Scratch memory is located in page 0 and is considered as the MMR for addressing.

65. Access Peripheral Registers
The I/O space is internal.
The PDP (Peripheral Data Pointer) register is used to access ports using direct addressing.
It is a 9bit register. Its value is concatenated with the 7 bits in the instruction to obtain a full 16-bit peripheral address.
The port() modifier selects the peripheral map

66. Access Peripheral Registers
I/O - Peripheral Memory Map
0000h
DMA
abs: MOV port(#addr),T1
dir: MOV #addr,PDP
MOV
indir: AMOV #addr,AR4
MOV port(*AR4),T1
McBSP
EHPI
EMIF
Timers
Power Dwn
Instr Cache
GPIO
FFFFh

67. Directives for Addressing Modes
3 Mode bits affect addressing:
ARMS: Address Register Mode Select
C54CM: C54 Compatibility Mode
C54CM=1 on reset, native C55x coding requires C54CM=0.
CPL: ComPiLer Mode
3 directives help the assembler to check the syntax and responds with ERROR in case of inconsistency:
.arms_on or .arms_off
.c54cm_on or .c54cm_off
.cpl_on or .cpl_off

68. Modifying Status Bits BSET/BCLR bit_name BCLR ARMS ;clear ARMS
BSET CPL ;set CPL
BCLR C54CM ;clear C54CM
We really don’t use this capability in the lab because the bits that affect addressing modes come out of reset in the correct fashion. However, we consider this an important topic and actually use this addressing capability in future modules. Nevertheless, it is good programming practice to ensure that the status bits are initialized to known values.
Make sure that you explain, at this point, that this is the way to set/clr bits in STATUS REGISTERS ONLY. You can also set bits in memory and CPU registers (like Tx, ARx and ACx). We will cover how this is done later. This format of setting/clearing bits is ONLY for status registers.

69. Addressing Exercise .dp x 21h XAR1 02_0106h 30h 40h XDP 02_0106h 50h
The initial state of each instruction is shown here...
Below, write down the state after each instr
02_0105h
21h
XAR1
02_0106h
x = 02_0106h
30h
02_0107h
40h
XDP
02_0106h
02_0108h
50h T0 2
.dp x
02_0206h
60h

70. Addressing Exercise – Solution
The initial state of each instruction is shown here...
Below, write down the state after each instr
02_0105h
21h
XAR1
02_0106h
x = 02_0106h
30h
02_0107h
40h
XDP
02_0106h
02_0108h
50h T0 2
.dp x
02_0206h
60h

72. Circular buffer and circular addressing
A circular buffer of length N is a block of contiguous memory words addressed by a pointer using a modulo N addressing mode.
The 2 extreme words of the memory block are considered as contiguous.
Characteristics of a circular buffer:
Instead of moving the N data in memory, just modify the pointers.
When a new data x(n) arrives, the pointer is incremented and the new data is written in place of the oldest one.

73. Trace of Memory and Pointer in a Circular Buffer of Length 3
Very often used for FIR filters.