1. UNIT 2:BEHAVIOURAL MODELING
What is behavioural modeling
What are the Verilog constructs for behavioural modelling: Structured Procedures, Procedural Assignments
(keywords) -initial & always
Statements used in behavioural modeling
Procedural assignment
Blocking vs. Non-blocking
Conditional statements:if and else
Multiway branching: ( case, casex, casez)statements
Loops(while, for, repeat, forever)
Timing and control : by delays, events, and level
Sequential and parallel blocks
Generate blocks
Task and functions
Behavioral modeling of sequential logic modules: Latches, Flip Flops, counters and shift registers applications
Design of Mealy and Moore FSM models for sequence detector using Verilog. Logic Synthesis, Synthesis Design Flow, Gate level netlist. PROGRAMS : ALU,ENCODER,DECODER,MUX,DEMUX,PARITY CHECKER

2. The move toward higher abstractions:
Gate-level modeling
Netlist of gates
Dataflow modeling
Boolean function assigned to a net
Now, behavioral modeling also called ALGORITHIMIC MODELING
A sequential algorithm (quite similar to software) that determines the value(s) of variable(s)

3. Behavioral Modeling

4. Behavioral Modeling
Behavioral modeling represents digital circuits at a functional and algorithmic level.
It is used mostly to describe sequential circuits, but can also be used to describe combinational circuits.
Behavioral descriptions use the keyword always followed by a list of procedural assignment statements.
The target output of procedural assignment statements must be of the reg data type.
A reg data type retains its value until a new value is assigned.

5. Structured Procedures
A module may contain multiple always statements and multiple initial statements.
Each statement starts a separate control flow and starts execution at time 0.

6. Structural Procedural Blocks
The basis for behavioral modeling is the procedural block:
Procedural Blocks are constructed from the following components.
Procedural Assignment Statements: initial & always
High-Level Constructs

7. Structured Procedures: initial statement
Starts at time 0
Executes only once during a simulation
Multiple initial blocks, execute in parallel
All start at time 0
Each finishes independently
Syntax:
initial
begin
// behavioral statements
end

8. Structured Procedures: initial statement (cont’d)
Example:
module stimulus;
reg x, y, a, b, m;
initial
m= 1’b0;
begin
#5 a=1’b1;
#25 b=1’b0;
end
#10 x=1’b0;
#25 y=1’b1;
initial
#50 $finish;
endmodule

9. Structured Procedures: always statement
Start at time 0
Execute the statements in a looping fashion
Example
module clock_gen;
reg clock;
// Initialize clock at time zero
initial
clock = 1’b0;
// Toggle clock every half-cycle (time period =20)
always
#10 clock = ~clock;
#1000 $finish;
endmodule

10. Difference between initial and always block
Starts when simulation starts … in arbitrary order
Execute once and stop
Continually loop— while (power on) do statements;
No, used as testbench
Yes, used in synthesis
Statement
Starts
How it works
Use in Synthesis?
Looks like
begin …
end
In a tabular cloumn write the differences & Mention the example here from the previous slides/class notes in the last in a tabular column

11. Procedural Assignments
It update the values of reg,integer,real or time variables.
The LHS of a prpcedural assignment <value>
Syntax
Assignment::=variable_1value=[delay/event control] expression
The LHS of a procedural assignment <1value> can be
reg, integer, real, time
A bit-select of the above (e.g., addr[0])
A part-select of the above (e.g., addr[31:16])
A concatenation of any of the above
<expression> is the same as introduced in dataflow modeling

12. Procedural Assignments

13. Continuous assignment(dataflow) vs Procedural assignment(behavioral)
Occurs within a module.
Executes concurrently with other statements ; executes whenever there is a exchange of value in an operand on its right-hand side.
Drives nets.
Uses “ = “ assignment symbol.
Uses assign keyword
Procedural assignment
Occurs inside an always statement or an initial statement.
Execution is with respect to other statements surrounding it.
Drives registers.
Uses “ = “ or “ < = “ assignment symbol.
No assign keyword

14. Blocking Procedural Assignments
The two types of procedural assignments
Blocking assignments(= operator specify the blocking assignment)
Non-blocking assignments(<= operator specify the nonblocking assignment)
Blocking assignments
are executed in order they are specified in a sequentially block.
A blocking assignment will not block execution of statement that follow in parallel block.
Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial begin
x=0; y=1; z=1;scalar assignments
count=0; reg_a= 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1;
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
end

15. Non-Blocking Procedural Assignments
Non-blocking assignments
Processing of the next statements is not blocked for this one
Allows scheduling of assignments without blocking excution of the statements that follow in sequential block.
Transactions created sequentially (in order), but executed after all blocking assignments in the corresponding simulation cycle
Syntax:
<lvalue> <= <expression>
EXAMPLE: FROM NOTES PLS REFER

16. Non-Blocking Assignments (cont’d)
Thus the simulator schedules a non blocking assignment statement to execute and continues to next statement in the block without waiting to complete the previous execution
Application of non-blocking assignments
Used to model concurrent data transfers
Example: Write behavioral statements to swap values of registers a & b at positive clock edge using two concurrent always blocks
clock)
a=b; Blocking
b=a;
a<=b;
clock) Non-blocking
b<=a;

17. Differences between blocking & Non blocking
Procedural assignments are of 2 types:
Non-blocking assignment
Blocking assignment
done by (=) operator
completed in one pass:
RHS expression is evaluated and stored in LHS register
assignments are executed in the order specified
Used to represent combinational ckts
done by the (<=) operator
done in two passes:
Evaluation of the RHS expressions first
Assignment of LHS next
assignments are scheduled without blocking execution of statements
Used to represent sequential ckts
Write the examples mentined in the class here 17

18. Example 7-8 Nonblocking Statements to Eliminate Race Conditions (Continued…)
//Illustration 1: Two concurrent always blocks with blockingstatements
clock)
a = b;
clock)
b = a;
//Illustration 2: Two concurrent always blocks with nonblocking
//statements
a<= b;
b<= a;
 In Example 7-8, in Illustration 1, there is a race condition when blocking statements are used. Either a = b would be executed before b = a, or vice versa, depending on the simulator implementation. Thus, values of registers a and b will not be swapped. Instead, both registers will get the same value (previous value of a or b), based on the Verilog simulator implementation.
 However, nonblocking statements used in Illustration 2 eliminate the race condition. At the positive edge of clock, the values of all right-hand-side variables are "read," and the right-hand-side expressions are evaluated and stored in temporary variables. During the write operation, the values stored in the temporary variables are assigned to the left-hand- side variables. Separating the read and write operations ensures that the values of registers a and b are swapped correctly, regardless of the order in which the write operations are performed..

19. Timing and Control in Behavioral modeling
Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no timing control statements, the simulation time does not advance. Timing controls provide a way to specify the simulation time at which procedural statements will execute.
There are three methods of timing control:
1.Delay-based timing control: 
Regular delay control
Intra-assignment delay control
Zero-delay control
2.Event-based timing control:
Regular event control
Named event control
iii. Event OR control
3.Level-sensitive timing control-Wait keyword

20. 1.Delay-based timing control: 
Regular delay control :Regular delay control is used when a non-zero delay is specified to the left of a procedural assignment
//define register variables reg x, y, z, p, q;
 initial begin
x = 0; // no delay control
#10 y = 1; // delay control with a number. Delay execution of y = 1 by 10 units
#(4:5:6) q = 0; // min,typical and max value delay
ii.Intra-assignment delay control :Instead of specifying delay control to the left of the assignment, it is possible to assign a delay to the right of the assignment operator [variable = #Δt expression;]
//define register variables reg x, y, z;
 //intra assignment delays initial
begin
x = 0; z = 0;
y = #5 x + z; //Take value of x and z at the time=0, evaluate x + z and then wait 5 time units to assign value to y.
iii.Zero delay control : it is a method to ensure that a statement is executed last, after all other statements in that simulation time are executed
initial begin
#0 x = 1; //zero delay control #0 y = 1;// execute at last statement
end

21. 2. Event based :An event is the change in the value on a register or a net. Events can be utilized to trigger execution of a statement or a block of statements(reactive behavior/reactivity)
• Events to specify:
• posedge sig: • Change of sig from any value to 1or from 0 to any value
• negedge sig: • Change of sig from any value to 0or from 1 to any value
• sig: Any chage in sig value
i.Regular event symbol is used to specify regular event control
@(clock) q = d; //q = d is executed whenever signal clock changes value
@(posedge clock) q = d; //q = d is executed whenever signal clock does a positive transition ( 0 to 1)
ii. Named event control: You can declare (name) an event, and then trigger and recognize it.
event received_data; //Define an event called received_data
clock) //check at each positive clock edge begin
if(last_data_packet) //If this is the last data packet->received_data; //trigger the event received_data
End
iii. Event OR Control:Sometimes a transition on any one of multiple signals or events can trigger the execution of a statement or a block of statements. This is expressed as an OR of events or signals. The list of events or signals expressed as an OR is also known as a sensitivity list
//A level-sensitive latch with asynchronous reset
reset or clock or d)
begin 
 if (reset) //if reset signal is high
else if(clock) //if clock is high,
q = d;

22. 3.Level-Sensitive Timing Control
NOTE: When the number of input variables to a combination logic block are very large, sensitivity lists can become very cumbersome to write. Moreover, if an input variable is 
missed from the sensitivity list, the block will not behave like a combinational logic block. To solve this problem, Verilog HDL contains two special
3.Level-Sensitive Timing Control
Verilog also allows level- sensitive timing control, that is, the ability to wait for a certain condition to be true before a statement or a block of statements is executed. The keyword wait is used for level- sensitive constructs.
always
wait (count_enable) #20 count = count + 1;
In the above example, the value of count_enable is monitored continuously. If count_enable is 0, the statement is not entered. If it is logical 1, the statement count = count + 1 is executed after 20 time units. If count_enable stays at 1, count will be incremented every 20 time units.

23. Conditional Statements
Conditional statements are used for making decisions based upon certain conditions. These conditions are used to decide whether or not a statement should be executed. Keywords if and else are used for conditional statements. There are three types of conditional statements
//Type 1 conditional statement. No else statement.
//Statement executes or does not execute. if (<expression>) true_statement ;
//Type 2 conditional statement. One else statement
//Either true_statement or false_statement is evaluated if (<expression>) true_statement ; else false_statement ;
//Type 3 conditional statement. Nested if-else-if.
//Choice of multiple statements. Only one is executed.
if (<expression1>) true_statement1 ;
else if (<expression2>) true_statement2 ; else if (<expression3>) true_statement3 ; else default_statement ; 23

24. Behavioral Modeling Statements: Conditional Statements
Just the same as if-else in C
Syntax:
if (<expression>) true_statement;//type 1
if (<expression>) true_statement;//type 2
else false_statement;
if (<expression>) true_statement1;// type 3
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;
True is 1 or non-zero
False is 0 or ambiguous (x or z)
More than one statement: begin end

25. Conditional statements:
The if and if-else statements
if and if-else Statements:
The if and if-else statements are the most common branching statements.
Syntax:
if ( expression )
statement or null;
else

26. Examples Example 1: Example 2: if (sel) if (sel==3) y = b; y = d; else
y = a;
if (sel==3)
y = d;
else if (sel==2)
y = c;
else if (sel==1)
y = b;
else if (sel==0)
y = a; 26

27. Looping Statements The for loop The forever loop The repeat loop
The while loop 27

28. for loop
Syntax:
for ( assignment ; expression ; assignment ) statement
The simulator performs the initial assignment
The simulator evaluates the expression and exits the loop if it is not true
The simulator executes the statement
The simulator executes the second assignment
Example :
integer count;
initial
for ( count=0; count < 128; count = count + 1)
$display("Count = %d", count); 28

29. forever Loop
A forever loop executes a statement (or block of statements) until the simulation ends.
A forever loop should be the last item in a sequential begin-end block, as the simulator cannot execute any statements following it.
Example :
// Clock
reg clk;
initial
begin
clk = 0;
forever
#10 clk = 1;
#10 clk = 0;
end 29

30. repeat Loop
A repeat loop executes a block of statements a fixed number of times.
Syntax:
repeat ( expression ) statement
Example:
//Illustration 1 : increment and display count from 0 to 127
integer count;
initial
begin
count = 0;
repeat(128)
$display("Count = %d", count);
count = count + 1;
end 30

31. while Loop
A while loop executes a statement (or block of statements) as long as its expression is known and nonzero.
If the expression is initially false, the statements are not executed.
Syntax: while ( expression ) statement
Example:
//Increment count from 0 to 127. Exit at count 128
integer count;
initial
begin
count = 0;
while (count < 128) //Execute loop till count
is 127 and exit at count128
count = count + 1;
end 31

32. Sequential and Parallel Blocks

33. Block Types There are two types of blocks: sequential blocks and parallel blocks.
Sequential blocks The keywords begin and end are used to group statements into sequential blocks.
Used to group multiple statements
Sequential blocks
Keywords: begin end used to group multiple statements
Statements are processed in order.
A statement is executed only after its preceding one completes
Thus, we used sequential blocks where the statements in the block execute one after another.

34. //Illustration 1: Sequential block without delay
reg x, y;
reg [1:0] z, w;
initial
begin
x = 1'b0;
y = 1'b1;
z = {x, y};
w = {y, x};
end
//Illustration 2: Sequential blocks with delay.
x = 1'b0; //completes at simulation time 0
#5 y = 1'b1; //completes at simulation time 5
#10 z = {x, y}; //completes at simulation time 15
#20 w = {y, x}; //completes at simulation time 35

35. Parallel Blocks
Keywords: fork, join
Statements in the blocks are executed concurrently
Timing controls specify the order of execution of the statements
All delays are relative to the time the block was entered
The written order of statements is not important
The join is done when all the parallel statements are finished
FUNDAMENTAL DIFFERENCE B/W squential & parallel blocks is that all statements in a parallel block start at the time when the block was entered. Thus the order in which the statemnets are written is not important.
Write the differences between them in a tabular column with example at the last explained in the class

36. Parallel blocks
Parallel blocks, specified by keywords fork and join, provide interesting simulation features. Parallel blocks have the following characteristics:
• Statements in a parallel block are executed concurrently.
• Ordering of statements is controlled by the delay or event control assigned to each
statement.
• If delay or event control is specified, it is relative to the time the block was
entered.
Notice the fundamental difference between sequential and parallel blocks. All statements in a parallel block start at the time when the block was entered. Thus, the order in which the statements are written in the block is not important.
//Example 1: Parallel blocks with delay.
reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0; //completes at simulation time 0
#5 y = 1'b1; //completes at simulation time 5
#10 z = {x, y}; //completes at simulation time 10
#20 w = {y, x}; //completes at simulation time 20
join

37. Sequential vs. Parallel Blocks
initial
begin
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
#20 w={y,x};
end
initial
fork
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
#20 w={y,x};
join
DSD
DSD 37

38. Sequential and parallel blocks can be mixed
initial
begin
x=1’b0;
fork
#5 y=1’b1;
#10 z={x,y};
join
#20 w={y,x};
end

39. Behavioral Modeling Statements: Multiway Branching(case,casex & casez) statements
Similar to switch-case statement in C
Keywords case,endcase and default are used in the case statement.
Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase
Notes:
<expression> is compared to the alternatives in the order specified.
Default statement is optional

40. Multiway Branching
case Statement The keywords case, endcase, and default are used in the case statement.. case (expression) alternative1: statement1; alternative2: statement2; alternative3: statement3; ... default: default_statement; endcase Each of statement1, statement2 , default_statement can be a single statement or a block of multiple statements. A block of multiple statements must be grouped by keywords begin and end. The expression is compared to the alternatives in the order they are written. For the first alternative that matches, the corresponding statement or block is executed. If none of the alternatives matches, the default_statement is executed.

41. casex, casez Keywords
There are two variations of the case statement. They are denoted by keywords, casex and casez.
• casex and casez keywords
casez treats all z values as “don’t care”
casex treats all x and z values as “don’t care”
The use of casex and casez allows comparison of only non-x or -z positions in the case expression and the case alternatives.
reg [3:0] encoding;
integer state;
casex (encoding) //logic value x represents a don't care bit.
4'b1xxx : next_state = 3;
4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
4'bxxx1 : next_state = 0;
default : next_state = 0;
endcase

42. Cont… Example: Syntax: case ( expression ) case_item ... endcase
case Statement:
does a bit-by-bit comparison for an exact match (including x and z).
automatically breaks after the first match
Example:
Syntax: case ( expression ) case_item ... endcase
(a,b,c,d,sel)
begin
case (sel)
3: y = d;
2: y = c;
1: y = b;
default: y = a;
endcase
end
Note: default statement detects unexpected values and is optional 42

43. always @(s1 or s0 or i0 or i1 or i2 or i3 or i4…i63) (*)
EXAMPLE : 4:1 MUX USING CASE STATEMENT
module mux4_to_1 (i0, i1, i2, i3, s1, s0,out);// Port declarations from the I/O diagram
input i0, i1, i2, i3;
input s1, s0;
Output reg out;
or s0 or i0 or i1 or i2 or i3 or i4…i63) (*)
case ({s1, s0}) //Switch based on concatenation of control signals
2‘b00 : out = i0;
2‘b01 : out = i1;
2‘b10 : out = i2;
2‘b11 : out = i3;
default: $display("Invalid control signals");
Endcase
endmodule

44. EXAMPLE USING CASE STATEMEMT: ALU DESIGN
//Execute statements based on the ALU control signal reg [1:0] alu_control;
...
case (alu_control)
2‘b00 : y = x + z;
2‘b01 : y = x - z;
2‘b10 : y = x * z;
default : $display("Invalid ALU control signal"); endcase

45. Example 7-20 Case Statement with x and z
 The case statements compare <expression> and alternatives bit-for-bit
x and z values should match
module demultiplexer1_to_4 (in, s1, s0, out0, out1, out2, out3, );
 // Port declarations from the I/O diagram output out0, out1, out2, out3;
input in;
input s1, s0;
Output reg out0, out1, out2, out3;
or s0 or in) /
case ({s1, s0}) //Switch based on control signals cancatenation
2'b00 : begin out0 = in; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
2'b01 : begin out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end
2'b10 : begin out0 = 1'bz; out1 = 1'bz; out2 = in; out3 = 1'bz; end
2'b11 : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = in; end
endcase
endmodule

46. Procedures/Subroutines/Functions in S/W programming languages
TASKS AND FUNCTIONS:
Procedures/Subroutines/Functions in S/W programming languages
The same functionality, in different places
Verilog equivalence:
Tasks and Functions
Used in behavioral modeling
Part of design hierarchy  Hierarchical name

47. Tasks & Functions
A group of statements that are kept in block and that block is called several times to perform specific task/function in the code.
TASK:
A task is defined within a module definition. It is defined within task and endtask keywords
A task can have input, output, and inout ports.
We can design combinational and sequential ckts. & both blocking and non-blocking assignments we can use.
Keywords: task, endtask
Must be used if the procedure has
any timing control constructs
zero or more than one output arguments
no input arguments
SYNTAX:
task <task_name>;
<I/O declarations> // optional
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask

48. Functions
A function is defined within a module definition and within function and endfunction keywords
A function by default returns a scalar reg.
A function must have at least one input (one argument) and may not have an output or inout.
It can be used only for designing combinational ckts
Used only blocking assignments
Keyword: function, endfunction
Can be used if the procedure:
does not have any timing control constructs
returns exactly one single value(advantage of function)
has at least one input argument
Syntax:
function <range_or_type> <func_name>;
input <input argument(s)> // at least one input
<variable_declaration(s)> // optional
begin // if more than one statement needed
<statements>
end // if begin used
endfunction

49. Difference between task and function

51. Generate Blocks
Generate statements allow Verilog code to be generated dynamically at elaboration time before the simulation begins.
Generate statements allow control over the declaration of variables, functions, and tasks, as well as control over instantiations. All generate instantiations are coded with a module scope and require the keywords generate – endgenerate.
Generated instantiations can be one or more of the following types:
• Modules
• User defined primitives
• Verilog gate primitives
• Continuous assignments
• initial and always blocks
There are three methods to create generate statements
• Generate loop
• Generate conditional
• Generate case

52. Generate statements are convenient when the same operation/module
Instance is repeated for multiple bits of a vector or when a certain Verilog
Code is conditionally included based on parameter definitions.
Generate statements allows control over the declarations of variables, functions, tasks and over instantiations. Its requires the keywords: generate-endgenerate.
Ex: Generate Ripple adder
module ripple adder(a,b,cin,sum,carry);
parameter N=4; //4 BIT BUS STRUCTURE BY DEFAULT
input [N-1:0]=a,b;
input cin;
output carry;
output [N-1:0]=sum;
Wire w1,w2,w3;
genvar i;
generate for(i=0;i<N;i++)
begin:r_loop
xor g1(w1,a,b);
xor g2(sum,cin,w1);

53. and g3(w2,a,b);
and g4(w3,b,c);
or g5(carry,w1,w2);
end
endmodule
For the above generate loop, the following instance are generated:
xor:r_loop[0].g1,r_loop[1].g1,r_loop[2].g1,r_loop[3].g1;
r_loop[0].g2,r_loop[1].g2,r_loop[2].g2,r_loop[3].g2;
and:r_loop[0].g3,r_loop[1].g3,r_loop[2].g3,r_loop[3].g3;
r_loop[0].g4,r_loop[1].g4,r_loop[2].g4,r_loop[3].g4;
or:r_loop[0].g5,r_loop[1].g5,r_loop[2].g5,r_loop[3].g5;

54. Logic synthesis is the process of converting a high-level description of design into an optimized gate-level representation. Logic synthesis uses a standard cell library which have simple cells, such as basic logic gates like and, or, and nor, or macro cells, such as adder, muxes, memory, and flip-flops. Standard cells put together are called technology library. Normally the technology library is known by the transistor size (0.18u, 90nm).

55. BUS STRUCTURE

56. Dataflow Modeling (3)
// Dataflow description of 2-bit comparator ( in the lab)
//Dataflow description of a 4-bit comparator.
module magcomp (A,B,ALTB,AGTB,AEQB);
input [3:0] A,B;
output ALTB,AGTB,AEQB;
assign ALTB = (A < B),
AGTB = (A > B),
AEQB = (A == B);
endmodule
Test bench: write yourself
Structural/Hierarchical modeling description of a 4-bit comparator.
// instantiation of 2-bit comparator design must be called in the top module (4 –bit comparator)
See the lab program
Structural/Hierarchical modeling description of a 8-bit comparator
// instantiation of 4-bit comparator design must be called in the top module (8 –bit comparator)

57. Dataflow Modeling :-2:1 MUX using conditional operator & using assign
Dataflow Modeling provides the means of describing combinational circuits by their function rather than by their gate structure.
Conditional operator (?:)
condition ? true-expression : false-expression;
A 2-to-1 line multiplexer
assign OUT = select ? A : B;
//Dataflow description of 2-to-1-line mux
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
OUT=SBAR.A+ S.B
//assign out= (A&S)|(A&S);

58. Behavioral Modeling :- 2:1 Mux
The procedural assignment statements inside the always block are executed every time there is a change in any of the variable listed after symbol. (Note that there is no “;” at the end of always statement)
//Behavioral description of 2-to-1-line multiplexer
module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule

59. 4-to-1 Multiplexer – Data Flow
//4-to-1 Mux: Dataflow description
module mux_4_to_1(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
assign Y = (~S[1]&~S[0]&D[0])|(~S[1]&S[0]&D[1]) |(S[1]&~S[0]&D[2])|(S[1]&S[0]&D[3]);
endmodule
//4-to-1 Mux: Conditional Dataflow description
module mux_4_to_1(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
assign Y = (S==2’b00)?D[0] : (S==2’b01)?D[1] : (S==2’b10)?D[2] : (S==2’b11)?D[3]:1’bx;;
endmodule

60. 4-to-1 Multiplexer

61. //4-to-1 Mux: GATE LEVEL MODELING
module mux_4_to_1_st_v(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
wire [1:0]N;
Write yourself
endmodule

62. Behavioral Modeling (4)
//Behavioral description of 4-to-1 line mux
module mux4x1_bh (i0,i1,i2,i3,select,y);
input i0,i1,i2,i3;
input [1:0] select;
output reg y;
or i1 or i2 or i3 or select)
case (select)
2'b00: y = i0;
2'b01: y = i1;
2'b10: y = i2;
2'b11: y = i3;
endcase
Endmodule
In 4-to-1 line multiplexer, the select input is defined as a 2-bit vector and output y is declared as a reg data.
The always block has a sequential block enclosed between the keywords case and endcase.
The block is executed whenever any of the inputs listed after symbol changes in value.

63. 1: 4 DEMUX GATE LEVEL
0,1

64. 1:4 DEMUX USNG CASE
(i or s0 or s1)
case ({s1,s0})
    0: out0 = i;
    1: out1 = i;
    2: out2 = i;
    3: out3 = i;
    default: out = 4'bxxxx;
endcase endmodule

65. Z[0] =d;
………….
NOTE:REFER WORD DOCUMENT & VERILOG LAB MNAUAL FOR FURTHER PROGRAMS

66. Behavioral modeling of sequential logic modules: Latches, Flip Flops, counters and shift registers applications
Design of Mealy and Moore FSM models for sequence detector using Verilog. Logic Synthesis, Synthesis Design Flow, Gate level netlist. PROGRAMS : ALU,ENCODER,DECODER,MUX,DEMUX,PARITY CHECKER
WRITE YOURSELF FROM LAB MANUAL OR SOURCES