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Published bypraveena reddy Modified over 3 years ago
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Organization of a 1K* 1 memory chip
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Asynchronous DRAM Internal organization of a 2M*8 / (16 M) Dynamic memory chip
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Fast Page Mode Suppose if we want to access the consecutive bytes in the selected row. This can be done without having to reselect the row. Add a latch at the output of the sense circuits in each row. All the latches are loaded when the row is selected. Different column addresses can be applied to select and place different bytes on the data lines. Consecutive sequence of column addresses can be applied under the control signal CAS, without reselecting the row. Allows a block of data to be transferred at a much faster rate than random accesses. A small collection/group of bytes is usually referred to as a block. The block transfer capability is referred to as the fast page mode feature.
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Synchronous DRAM
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Latency, Bandwidth, and DDR SDRAMs Memory latency is the time it takes to transfer a word of data to or from memory Memory bandwidth is the number of bits or bytes that can be transferred in one second. DDR SDRAMs- Double Data Rate SDRAM Faster version Of SDRAM Transfer data on both edge of clock The latency is same but bandwidth is double..so DDR SDRAM Cell array is organized in two banks Applications: SDRAM & DDR SDRAM –where block transfer are Prevalent& used in high quality video displays
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