1. EEC 18 Lecture 4 Bevan M. Baas
Digital Systems I
EEC 18
Lecture 4
Bevan M. Baas

2. Minterm Example m0 m1
This circuit schematic shows all 8 minterms “present” for a 3-input combinational logic function
In practice, all possible minterms would never all be present in a circuit (do you see why?)
There is one possible minterm for each row in the truth table m2 m3 Z m4 m5 m6 m7

3. Minterm Example m0 1 m1
By construction, one and only one minterm is active (equals 1) at any point in time m2 m3 1 Z m4 m5 m6 m7

4. Minterm Example m0 1 m1 1
By construction, one and only one minterm is active (equals 1) at any point in time m2 m3 1 Z m4 m5 m6 m7

5. Minterm Example m0 1 m1
By construction, one and only one minterm is active (equals 1) at any point in time m2 1 m3 1 Z m4 m5 m6 m7

6. Minterm Example m0 1 1 m1
By construction, one and only one minterm is active (equals 1) at any point in time m2 m3 1 1 Z m4 m5 m6 m7

7. Minterm Example m0 1 m1
By construction, one and only one minterm is active (equals 1) at any point in time m2 m3 1 Z m4 1 m5 m6 m7

8. Minterm Example m0 1 1 m1
By construction, one and only one minterm is active (equals 1) at any point in time m2 m3 1 Z m4 m5 1 m6 m7

9. Minterm Example m0 1 1 m1 Z = m0 + m1 + m71 m1
Z = m0 + m1 + m7
To implement an expression, a circuit is built with only the present minterm(s)
The output can be 1 only when one of the present minterms forces the output to 1 m2 Z
nothing is here m7

10. Minterm Example m0 1 1 1 m1 Z = m0 + m1 + m71 1 m1
Z = m0 + m1 + m7
To implement an expression, a circuit is built with only the present minterm(s)
The output can be 1 only when one of the present minterms forces the output to 1 m2 1 Z m7 1

11. Minterm Example m0 1 1 1 m1 Z = m0 + m1 + m71 1 m1
Z = m0 + m1 + m7
Of course gate inputs can not be left unconnected (unspecified). There are two solutions:
Tie unused inputs to a value that disables those inputs. For an OR gate, inputs would be tied to 0 (or False or Gnd)
The best solution is to simplify the gate. In this example, the 8-input OR gate is simplified to a 3-input OR gate 1 Z m7 1