1. Reliability

2. Introduction Introduction to Reliability Historical Perspective
Current Devices
Trends

3. The Bathtub Curve (1) Failure rate,  Infant Mortality Useful life
Wear out
 Constant
Time

4. The Bathtub Curve (2) What is the "bathtub" curve?
In the 1950’s, a group known as AGREE (Advisory Group for the Reliability of Electronic Equipment) discovered that the failure rate of electronic equipment had a pattern similar to the death rate of people in a closed system. Specifically, they noted that the failure rate of electronic components and systems follow the classical “bathtub” curve. This curve has three distinctive phases:
1. An “infant mortality” early life phase characterized by a decreasing failure rate (Phase 1). Failure occurrence during this period is not random in time but rather the result of substandard components with gross defects and the lack of adequate controls in the manufacturing process. Parts fail at a high but decreasing rate.
2. A “useful life” period where electronics have a relatively constant failure rate caused by randomly occurring defects and stresses (Phase 2). This corresponds to a normal wear and tear period where failures are caused by unexpected and sudden over stress conditions. Most reliability analyses pertaining to electronic systems are concerned with lowering the failure frequency (i.e., const shown in the Figure) during this period.
3. A “wear out” period where the failure rate increases due to critical parts wearing out (Phase 3). As they wear out, it takes less stress to cause failure and the overall system failure rate increases, accordingly failures do not occur randomly in time.

5. Introduction to Reliability
Failure in time (FIT)
Failures per 109 hours
( ~ 104 hours/year )
Acceleration Factors
Temperature
Voltage

6. Introduction to Reliability (cont'd)
Most failure mechanisms can be modeled using the Arrhenius equation.
ttf - time to failure (hours)
C - constant (hours)
EA - activation energy (eV)
k - Boltzman's constant (8.616 x 10-5eV/°K)
T - temperature (ºK)
ttf = C • e
EA/kT

7. Introduction to Reliability (cont'd) Acceleration Factors
ttfL
A.F. =
ttfH
A.F. = acceleration factor
ttfL = time to failure, system junction temp (hours)
ttfH = time to failure, test junction temp (hours)

8. Introduction to Reliability (cont'd) Activation Energies
Failure Mechanism EA(eV)
Oxide/dielectric defects
Chemical, galvanic, or electrolytic corrosion 0.3
Silicon defects
Electromigration to 0.7
Unknown
Broken bonds
Lifted die
Surface related contamination induced shifts 1.0
Lifted bonds (Au-A1 interface)
Charge injection
Note: Different sources have different values - these values just given for examples.

9. Acceleration Factor - Voltage Oxides and Dielectrics
Large acceleration factors from increase in electric field strength
A.F. = 10 •  / (MV / cm)
k - Boltzman's constant (8.616 x 10-5eV/°K)
T - temperature (ºK)
 = • e
0.07/kT

10. Acceleration Factor: Voltage
Median-time-to-fail of unprogrammed antifuse vs. 1/V for different failure criteria with positive stress voltage on top electrode and Ta = 25 °C.

11. Device and Computer Reliability 1960's Hi-Rel Application
Apollo Guidance Computer
Failure rate of IC gates:
< 0.001% / 1,000 hours ( < 10 FITS )
Field Mean-Time-To-Failure
~ 13,000 hours
One gate type used with large effort on screening, failure analysis, and implementation.
NASA SP-8070
SPACE VEHICLE DESIGN CRITERIA
(GUIDANCE AND CONTROL)
SPACEBORNE DIGITAL COMPUTER SYSTEMS
MARCH 1971

12. Device Reliability:1971 Reliability Level of Representative
Parts and Practices MTBF (hr)
Commercial
Military ,000
High Reliability , (104 hours)

13. MIL-M-38510 Devices (1976) Circuit Types Description FITS
Quad, 2-input NAND
bit, full adder
bit, full adder
Dual, D, edge-triggered flip-flop
54S Hex, D, edge-triggered flip-flop
bit synchronous counter
4049A Inverting hex buffer
4013A Dual, D, edge-triggered flip-flop
4020A stage, ripple carry counter
Triple NOR (ECL)
HYPROM bit PROM

14. Harris CICD Devices (1987) Circuit Types
HS k X 1 RAM HS-8155/ x 8 RAM
HS k x 4 RAM HS-82C08RH - Bus Transceiver
HS-3374RH - Level Converter HS-82C12RH - I/O Port
HS-54C138RH - Decoder HS-8355RH - 2k x 8 ROM
HS-80C85RH - 8-bit CPU
Package Types
Flat Packs (hermetic brazed and glass/ceramic seals)
LCC
DIP
55°C, Failure 60% U.C.L.
43.0

15. UTMC and Quicklogic FPGA UT22VP10 Antifuse PROM < 10 FITS (planned)
Quicklogic reports 12 FIT, 60% UCL
UT22VP10
UTER Technology, 0 failures, 0.3 [double check]
Antifuse PROM
64K: 19 FIT, 60% UCL
256K: 76 FIT, 60% UCL

16. Xilinx FPGAs XC40xxXL XCVxxx Static: 9 FIT, 60% UCL
Dynamic: 29 FIT, 60% UCL
XCVxxx
Static: 34 FIT, 60% UCL
Dynamic: 443 FIT, 60% UCL

17. Actel FPGAs Technology FITS # Failures Device-Hours
2.0/ x 107
x 108
x 108
x 108
x 107
x 107
RTSX x 107
x 107
x 107

18. RAMTRON FRAMs Technology FITS # Failures # Devices Hours Device-Hours
1608 (64K)
4k & 16K
Serial x 106
Note: Applied stress, HTOL, 125ºC, Dynamic, VCC=5.5V.
1 The one failure occurred in less then 48 hours. The manufacturer feels that this was an infant mortality failure.
2 12 failures detected at 168 hours, 3 failures at 500 hours, and no failures detected after that point.

19. Actel FIT Rate Trends

20. Skylab Lessons Learned
58. Lesson: New Electronic Components
Avoid the use of new electronic techniques and components in critical subsystems unless their use is absolutely mandatory.
Background:
New electronic components (resistors, diodes, transistors, switches, etc.) are developed each year. Most push the state-of-the-art and contain new fabrication processes. Designers of systems are eager to use them since they each have advantages over more conventional components. However, being new, they are untried and generally have unknown characteristics and idiosyncracies. Let some other program discover the problems. Do not use components which have not been previously used in a similar application if it can be avoided, even at the expense of size and weight.
These lessons learned are from SKYLAB LESSONS LEARNED AS APPLICABLE TO A LARGE SPACE STATION, A dissertation submitted to the faculty of The School of Engineering and Architecture Of the Catholic University of America For the Degree Doctor of Engineering by William C. Schneider, Washington,
D.C., 1976.

21. Reliability - Summary Covered device reliability basics
Design reliability is another set of topics
Advanced Design: Designing for Reliability
Fundamental Logic Design: Clocking, Timing Analysis, and Design Verification
Fundamental Logic Design: VHDL for High- Reliability Applications - Coding and Synthesis
Fundamental Logic Design: Verification of HDL- Based Logic Designs for High-Reliability Applications