1. Multiple-Input Gates VHDL
Discussion D1.2
Example 2

2. AND Gate
Behavior:
The output of an AND gate is HIGH only if all inputs are HIGH
z <= x(1) and x(2) and ... and x(n);

3. OR Gate
Behavior:
The output of an OR gate is LOW only if all inputs are LOW
z <= x(1) or x(2) or ... or x(n);

4. NAND Gate (NOT-AND) Behavior:
The output of an NAND gate is LOW only if all inputs are HIGH
z <= not(x(1) and x(2) and ... and x(n));

5. NOR Gate (NOT – OR) Behavior:
The output of an NOR gate is HIGH only if all inputs are LOW
z <= not(x(1) or x(2) or ... or x(n));

6. Exclusive-OR (XOR) Gate
Behavior:
The output of an XOR gate is HIGH
only if the number of HIGH inputs is ODD
z <= x(1) xor x(2) xor ... xor x(n);

7. Exclusive-NOR Gate XNOR (NOT – XOR)
Behavior:
The output of an XNOR gate is HIGH
only if the number of HIGH inputs is EVEN
z <= x(1) xnor x(2) xnor ... xnor x(n);

8. -- Example 2: 4-input gates
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity gates4 is
port(
x : in STD_LOGIC_VECTOR(4 downto 1);
z : out STD_LOGIC_VECTOR(6 downto 1) );
end gates4;
architecture gates4 of gates4 is
begin
z(6) <= x(1) and x(2) and x(3) and x(4);
z(5) <= not(x(1) and x(2) and x(3) and x(4));
z(4) <= x(1) or x(2) or x(3) or x(4);
z(3) <= not(x(1) or x(2) or x(3) or x(4));
z(2) <= x(1) xor x(2) xor x(3) xor x(4);
z(1) <= x(1) xnor x(2) xnor x(3) xnor x(4);

9. Aldec Active-HDL Simulation
and
nand or
nor
xor
xnor