1. Introduction to Electronic Design Automation
北京航空航天大学微电子学院
CADET实验室
成元庆 主讲

2. 集成电路EDA: 从RTL到GDSII
Week 1
Introduction and Motivation
Lecture 1
Background, EDA industry challenges
Lecture 2
Basics of algorithms and time complexity
Week 2
Graph Theory
Lecture 3
Graph traversals: DFS and BFS, application to maze routing
Lecture 4
Graph traversals: Topological search: application to static timing analysis
Week 3
Physical design – Circuit Partitioning
Lecture 5
Partitioning: Kernighan-Lin and Fidduccia-Mattheyses algorithms
Lecture 6
Week 4
Physical design – Floorplanning
Lecture 7
Floorplanning: slicing floorplans and sequence pairs
Lecture 8
Week 5
Physical design – Placement
Lecture 9
Analytic placement
Lecture 10
Analytic placement (Cont.)
Week 6
Physical design –Routing
Lecture 11
Global routing: Simultaneous routing, congestion estimation, machine learning methods
Lecture 12
Week 7
Making designs tolerant to process variations
Lecture 13
Congestion estimation, buffering algorithms
Lecture 14
Lithography, multiple patterning, ML methods
Week 8
Making designs tolerant to runtime variations
Lecture 15
Timing analysis under variations: corners, statistical analysis
Lecture 16
Backup
ML in EDA
Lecture 17
Role of machine learning in EDA
Lecture 18
Emerging Trends, Conclusion, and Summary

3. Timing Analysis

4. STA Review: Arrival Times
Assumptions:
All inputs arrive at time 0
All gate delays = 1
All wire delays = 0
Question: Arrival time of each gate? Circuit delay? 2 1 c 3 a f b 4 e g h 5 d
ti = max {tj} + di
[Bazargan]

5. STA Review: Required Times
Assumptions:
All inputs arrive at time 0
All gate delays = 1, wire delay = 0
Clock period = 7
Question: maximum required time (RT) of each gate? (i.e., if the gate output is generated later than RT, clk period is violated) 2 3 4 c 7 a 5 f 6 b e g h
ri = min {rj-dj } d
[Bazargan]

6. STA Review: Slack c a f b e g h d Assumptions:
All inputs arrive at time 0
All gate delays = 1, wire delay = 0
Clock period = 7
Question: What is the maximum amount of delay each gate can be slower not to violate timing?
2-0=2
3-0=3
5-0=5
3-1=2
4-2=2
5-3=2
6-1=5
6-4=2
7-4=3
7-5=2
7-3=4 c a f b e g h
si = ri-ti d
[Bazargan]

7. Static Timing Analysis
Problem
Given a transistor level description of combinational circuit, find arrival times at all gate outputs (pattern independent)
Solution
Clump transistors together into fundamental gates (“channel-connected components”)
Propagate timing information (low and high polarities from primary inputs (PI’s) to primary outputs (PO’s) (“critical path method (CPM)”)
Overcome miscellaneous hurdles along the way

8. Channel-connected Components
A set of transistors interconnected by drain/source nodes A B E C D A C B D E

9. From a Combinational Circuit to a DAG

10. The Critical Path Method (CPM)
Often (incorrectly) called “PERT” in the literature
• Place PI’s on a queue
• Process gate from head
of queue
• Add gate to queue if all
input delays known
• Complexity O(E)
• Can handle gate delay
dependence on order
of input arrivals a e 1 j 1 2 6 b f 3 9 l 3 3 i 1 4 c g 1 1 k d h 2 2 6 2

11. Incremental Analysis Event-driven analysis for minor changes
Propagate changes
by propagating events
incremental_analyze(g)
GATE g; {
if changes) {
arr_time = newvalue;
for (i  fanout(g))
incremental_analyze(i); }
Critical path may change!
2 1 a e 1 j 1
 b f 3 l 3 3 i 1 4 c g
 1 1 k d h 2 2 6 2

12. The Critical Path Method (CPM)
Often (incorrectly) called “PERT” in the literature
• Place PI’s on a queue
• Process gate from head
of queue, computing rise
and fall delays
Trise = maxinputs(Tfall+delay)
Tfall = maxinputs (Trise+delay)
• Add gate to queue if all
input delays known
• Complexity O(E) unchanged a e
2/1 j
2/1
4/2
3/1
3/2
8/5 b f
4/2 l
1/3 i
1/1
7/11 c g
3/5
3/1 k d h
2/2
4/2
7/6

13. False Paths (Briefly!) Classic example
Currently, no efficient automated methods for false path analysis exist
Case analysis with designer input is your best bet M U X 1 2 a b c

14. Sequential Circuits Setup Time Constraints Hold Time Constraints
Max clock skew
Max delay
Setup time
Min clock skew
Min delay
Hold time

15. Sequential Circuits: The Real Problem
Setup Time Constraints
Hold Time Constraints

16. CPPR/CRPR
“Common path pessimism reduction”/”Common reconvergence pessimism reduction”
Common part of launch/capture paths cannot have different delays: start launch/capture delay computation after removing common path

17. Classification of variations
Systematic/random, process/environmental
Systematic
Random
Process
(“one-time”)
Leff (lens aberration), Interlayer dielectric (pattern dependent)
Leff, tox, W, Vt, ρ
Environmental
(“run-time”)
Vdd variations, Temperature gradients, SOI history effects, Capacitive and inductive coupling, hot carriers, NBTI
EMI effects, alpha particles/soft errors

18. Sources of uncertainty in design
Operation
Applied signals
Power supply voltage
On chip voltage
Self heating
Device degradation
etc.
Design model
Approximations
Estimation errors in model assumptions
Changing reqisters, etc.
Manufacturing and packaging
Process change and drift
Systematic variation
Unassignable causes
[Hakim, Intel]

19. Uncertainty vs. deterministic nonuniformity
Random variations
Systematic effects
Deterministic nonuniformity
Modeled
deterministically? Y N
[Hakim, Intel]

20. Decomposition of CD variation patterns
Total CD Variation
Random component
Within-Die component
(systematic)
Within Wafer component
(systematic)
[Hakim, Intel]

21. Modeling random variation

22. Modeling random variations
Corner-based models/MCMM models
Statistical models
Parameters vary according to some probability density functions
[Wikipedia Commons]
[Wikipedia Commons]

23. Traditional corner-based analysis
Given a set of parameters p1, p2, … , pk
Each parameter varies between [pi,min, pi,max]
The variational region forms a multidimensional box
Corner-based analysis performs simulations at each corner
Typically parameters correspond to process parameters, temperature and voltage

24. The ellipsoid vs. the cuboid
Problem: how does one choose a corner?
3σ points? Along coordinate axes? At corners?
Locus of equiprobable points for most distributions is not a box
Gaussian: locus of equiprobable points forms an ellipsoid
Corner-based approach may be too pessimistic (or too optimistic)
Difference between ellipsoid and cuboid grows with dimensionality

25. Across-die vs. within-die variations

26. Statistical static timing analysis
Within-die variations in addition to across-die variations
Deterministic timing analysis  Statistical timing analysis
Path-based analysis: find variability along a single path
Block-based analysis: Find the distribution (PDF/CDF) of:
Dmax = max(D1, D2, … , Dnpaths)
Di: distribution of ith path delay PO D1 D2 PI
max(D1,D2…Dn) … …
Dnpath

27. Within-die vs. across-die variation
Flip-Flop … P
Dpath
Within-die P
Dpath
Across-die
Circuit delay is maximum of individual path delays
“Cancelations” due to within-die variations
[Blaauw]

28. Statisical cancelation on a path
[Jaeyon Chung,

29. Statistical spread across paths
Ncp = Number of Independent Critical Paths
As Ncp increases, WID distribution mean increases, variance decreases
[Intel]

30. Statistical static timing analysis (SSTA)
Path correlation due to reconvergent fanouts
Spatial correlations between nearby gates
Propagate probability distributions from inputs to outputs
a  b  d
Max func. of corr. paths b a d c
circuit delay distribution
a  c  d
Correlated paths

31. Commonly-encountered distributions
Gaussian or normal distribution N(𝜇,𝜎)
In one variable
PDF
CDF
For a Gaussian, independence is identical to uncorrelatedness [

32. Commonly-encountered distributions (contd.)
Bivariate Gaussian
PDF

33. Commonly-encountered distributions (contd.)
Multivariate Gaussian
PDF

34. Adding a set of Gaussians
The sum of two Gaussians is a Gaussian
Z= X+Y, where X, Y are uncorrelated Gaussians
Mean = 𝜇X + 𝜇Y
Variance
Also true for the sum of n Gaussians
Mean = sum of means
Variance = sum of variances
For n identical Gaussians
Mean 𝜇sum = n 𝜇
Variance 𝜎sum2 = n 𝜎2
So, (𝜇sum/ 𝜎sum) = (1/√n) (𝜇/ 𝜎)
In plain English:
The spread reduces due to cancelation

35. Corner-based margining
Flat global margin across the chip
Traditional on-chip variation (OCV) approach, timing derates are applied to scale the path delay by a fixed percentage
set_timing_derate –late 1.2; set_timing_derate –early 0.8
Common-path pessimism reduction (CPPR)
[Synopsys]

36. AOCV = advanced OCV Logic-depth-based derating Cell-based coefficients
[Synopsys]

37. AOCV (contd.)
Distance-based derating
Combined table
[Synopsys]

38. SOCV = Statistical OCV “SSTA-lite” for within-die variation
POCV (Parametric OCV) is similar
Mean, stdev of (delay, output slew) = f(load, input slew)
One value per timing arc
[Bautz/Lokanandham, TAU14]

39. Multimode multicorner design
Impractical to consider all corners, typically some corners dominate others
[Kahng, SRC Summer Study 2013]