1. Verilog Simulation Tools &Verification

2. Outline
NC-Verilog
nLint
nWave
Nicotb

3. NC-Verilog

4. Introduction to NC-Verilog
The Cadence® NC-Verilog® simulator is a Verilog digital logic simulator.
We can use NC-Verilog to
Compiles the Verilog source files.
Elaborates the design and generates a simulation snapshot.
Simulates the snapshot.

5. Before Using NC-Verilog
Source the environment settings of CAD tools.
If you try entering the command "ncverilog" but it turns out "command not found," it means there's something wrong with the "*.cshrc" file or the software license is out of date.
tool 2
source /usr/cad/cadence/CIC/incisiv.cshrc
有些server輸入"source ~cvsd/cvsd.cshrc"後會出現command not found
這很有可能是false alarm，先輸入ncverilog檢查是否能夠使用
如果可以使用的話就沒問題了

6. Running Verilog Run the Verilog simulation:
"+access+r" is added to enable waveform file dumping.
*.fsdb has smaller file size than *.vcd. But $fsdbDumpfile cannot work without sourcing verdi.cshrc.
ncverilog testbench.v design.v +access+r or

7. Simulation Results
Check the simulation result to see if the Verilog design is finished correctly.

8. nLint

9. Introduction to nLint
nLint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system (Developed by SpringSoft).
We can use nLint to check the coding style of our design and if it is synthesizable.

10. Start nLint Type the following command: nLint -gui & No gui command
The token "&" enable you to use the terminal while nLint is running in the background.
No gui command
nLint -gui &
nLint design.sv -sv -out screen
Just ignore this warning.

11. Specify the Design File1

12. 1 2 4 3 5

13. Start Checking 1

14. Not all the warnings or errors are valuable.

15. nWave

16. Introduction to nWave
nWave is one of the best waveform (*.vcd or *.fsdb) viewer.
We can debug easily by checking the waveform file dumped during simulation.

17. Start nWave Type the following command: nWave &
Also, the token "&" enable you to use the terminal while Verdi is running in the background.
nWave &
Just ignore this warning.

18. Open the FSDB File 1

19. 2 1 3

20. Choose Signals 1

21. 1 2
Choose signals we are interested in. 3 4

22. Browse the Whole Waveform1

23. Browse the Specified Interval
press & drag

25. Search for Specified Signal
4,5,… 2 3 1

26. Jump to the cursor position (Used when we are lost)
(Search by rising oe)

27. Change Sign Representation2 3 1

28. Change Radix Representation2 3 4 1

29. Leading zeros

30. Change Signal Position2
Press middle mouse button,
drag and then drop. 1

31. Signal Aliasing 2 1 3 4

32. 1 2 3
Note that signal aliasing is a strict one-to-one correspondence so the value represented in the viewer must exactly represent what format your filter expects. (e.g., binary, hexadecimal) 6 4 5

34. Reload the Waveform
Remember to reload the waveform whenever finishing another Verilog simulation.
Shift+L 1

35. Nicotb

36. What Forms Verification?
UVM (Universal Verfication Methodology).
(We usually call this overall platform as testbench.)
Your RTL
Generate Golden Data
Monitor output ports and collect data
Drive data to input ports

37. The Non-RTL Parts
The non-RTL parts can be implemented without Verilog!
This is usuallyed called co-simulation (co-sim).

38. Brief Conclusions - A Testbench Must
Instantiate (make a copy of) your module.
Driver to send data.
Monitor to receive and collect them.
Driver and Monitor might follow specific protocols.
The collected data are compared by Scoreboard.
Golden (Mostly text file in Verilog, or programmatically when co-simed.)
Generated by your RTL module and collected by Monitor.

39. No Need for Verify RTL with Verilog
Verilog provide external C accesses through VPI.
Based on C, people develops Java, Python... versions.
AFAIK, there are quite a lot Python based frameworks.
myhdl:
cocotb:
nicotb:
We focus on this today.

40. Bridging Python and Verilog (Events)
Add these lines in Python
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev",])
Add this lines in Verilog
`Pos(rst_out, rst) `PosIf(ck_ev, clk, rst)
This means, whenever a clk posedge in Python, ck_ev is triggered
Mostly your submodules use 1 reset and clock and you just copy it.
That is,
Python yield ck_ev = clk
However, simply writing yield in Python doesn't make thing easier.
We will explain later.

41. Bridging Python and Verilog (Wires)
API to connect Verilog wires
my_data_bus = CreateBus(( ("", "a_signal", (4,2)), ("dut", "sig"), ))
The Verilog to be connected
logic [7:0] a_signal [4][2]; DUT my_dut( .clk(clk), .sig(sig) )
hierarchy: toplevel → ""
name: a_signal
shape: (4,2)

42. Bridging Python and Verilog (Wires)
API to connect Verilog wires
my_data_bus = CreateBus(( ("", "a_signal", (4,2)), ("dut", "sig"), ))
The Verilog to be connected
logic [7:0] a_signal [4][2]; DUT dut( .clk(clk), .sig(sig) )
hierarchy: "dut" (nested: "dut.a.b")
name: sig
shape: not a array

43. Some Notes Make use of Python unpack easily.
a = CreateBus(A) b = CreateBus(B) c = CreateBus(C) a, b, c = CreateBuses([A, B, C])
This is the method of Nicotb, every framework has its method connecting Verilog to Python (or whatever).

44. Interface Reuse → Testbench Reuse
For example, your code:
module Dut( input clk, input rst, input irdy, output logic iack, input [10:0] iint, output logic ordy, input oack, output logic [10:0] oint );
You can test every module with the same API.
Input
Dut
Output
Dataflow graph.

45. Convert Bus into Protocol
First, you need to create the buses
irdy = CreateBus((("dut", "irdy"))) iack = CreateBus((("dut", "iack"))) iint = CreateBus((("dut", "iint"))) ordy = CreateBus((("dut", "ordy"))) oack = CreateBus((("dut", "oack"))) oint = CreateBus((("dut", "oint")))
Then, construct the classes in Python.
master = TwoWire.Master(irdy, iack, iint, ck_ev, A=1, B=5) slave = TwoWire.Slave( ordy, oack, oint, ck_ev, callbacks=[test.Get] )

46. Check at Scoreboard
Generate golden data for Scoreboard (not today's main issue).
Ns = np.array([0,8,7], dtype=np.int32) # this create a column vector [0, 0, 1, 2, ..., 8, 0, 1, ..., 7] golden = np.concatenate([ np.arange(N+1, dtype=np.int32) for N in Ns ])[:,np.newaxis] test.Expect((golden,))
What should I Expect?

47. Data Format in Nicotb Look at the data bus.
ordy = CreateBus((("dut", "ordy"))) oack = CreateBus((("dut", "oack"))) oint = CreateBus((("dut", "oint")))
Slave put that to Scoreboard.
st = Stacker(1+9+8, [bg.Get]) # PS: =18 bg = BusGetter(callbacks=[st.Get]) slave = TwoWire.Slave( ordy, oack, oint, ck_ev, callbacks=[bg.Get] )
oint is a bus with one scalar (aka, not an array), so you get a tuple of size ([18, 1],).
The actual code is slightly more complex than above pages, while you can just copy and modify.

48. Data Format in Nicotb Look at the data bus.
oint = CreateBus(( ("dut", "aaa") ("dut", "bbb", (1,)) ("dut", "ccc", (12,3)) ))
In this example, the tuple size is ([18, 1], [18, 1], [18, 12, 3]).

49. Back to Our Example Look at the data bus.
golden = np.concatenate([ np.arange(N+1, dtype=np.int32) for N in Ns ])[:,np.newaxis] test.Expect((golden,))
golden is a tuple of size ([18, 1],).
np.concatenate generate a array of size [18,], namely a row vector.
The [:, np.newaxis] is the standard method converting Numpy row vector to a column vector (vertical one).

50. We are Almost Done! O O O △ O X O O O O O X
Prepare the RTL for design under test (DUT).
Script for loading Python automatically (Makefile).
SystemVerilog wrapper.
Python testbench.
Prepare input data and golden (it's your task).
Send the data.
Check the data at scoreboard. O O △ O X O O O O O X

51. Drive Verilog Wire In Python (Quite Easy!)
master = TwoWire.Master(irdy, iack, iint, ck_ev, A=1, B=5)
values = master.values
def it():
for N in Ns:
values.iint[0] = N
yield values
yield from master.SendIter(it())
yield from master.SendIter(it(), latency=100)
Probability = A/B (default = 1/5)
Access data bus by name
values.iint is a Numpy array of size (1,)
This randomly drive the input.
This drive data every 100 cycles.

52. Note
values = master.values
def it():
for N in Ns:
values.iint[0] = N
yield values
yield from master.SendIter(it())
yield from master.SendIter(it(), latency=100)
This part is only Python generator syntax, it has no relationship with waiting Verilog posedge!!!
Every 100 cycles (ignore probability)

53. Prepare a Verilog Wrapper
`Pos(rst_out, rst) `PosIf(ck_ev, clk, rst) always #1 clk = ~clk; initial begin clk = 0; rst = 1; #1 $NicotbInit(); #11 rst = 0; #10 rst = 1; #1000 $display("Timeout"); $NicotbFinal(); $finish; end assign oack = ordy && ocanack; Dut dut(clk,rst,irdy,iack,iint,ordy,oack,oint);
Declare your module here!
While you might not understand it, this template requires almost no modifications!
Declare your module here!

54. (Prepare a Makefile) Modify according to your path (irun = ncverilog)
NICOTB=~/nicotb/lib
IRUN=/opt/CAD/INCISIV/cur/tools.lnx86/bin/64bit/irun
%: %.sv
GLOG_logtostderr=1 \
TEST=$(if \
TOPMODULE=$(if \
PYTHONPATH=$(NICOTB)/python:`pwd` \
$(IRUN) +access+rw -loadvpi $(NICOTB)/cpp/nicotb.so:VpiBoot \ $(NICOTB)/verilog/Utils.sv $<
You must prepare XXX_test.py and XXX_test.sv under current directory (see previous pages). Also, the top level testbench module is XXX_test.
Then, just type make XXX. The lab in these days is an example.

55. Conclusions Introduce the idea behind SystemVerilog UVM.
With Python, you can do the same thing much easily.
We introduce Nicotb today.
Document:
And there are many choices.
myhdl:
cocotb:

56. The End