EE222_Lecture 5 On-Chip Power Distribution Network January 23, 2018

EE222_Lecture 5 On-Chip Power Distribution Network January 23, 2018
Reference: Prof. E. G. Friedman, Univ. of Rochester

National vs Chip Level Power Grids
US Power Distribution System IC Power Distribution Grid Low voltage High voltage Area – 9,629,091 km2 Area – 6.45 cm2 (1 in2) 10 metal layers Line width – 150 m to 15 km Interlayer spacing – 200 m to 1000 m Scale factor 1.5 x 108 10 metal layers Line width – 1 μm to 100 μm Interlayer spacing – 2 μm to 10 μm

Macro vs Micro Power Delivery
Regional Power Distribution System IC Power Distribution System Vdd Iload Board Package Integrated circuit Voltage regulator Four level of hierarchy Voltage scaled to lower losses Simple interconnect structure Long distance power delivery Four level of hierarchy Dimensions scaled to lower losses Sophisticated interconnect structure Short distance power delivery

On-Chip Power Distribution Networks in High Speed Integrated Circuits
Agenda Motivation On-chip power distribution networks Computer-aided design and analysis Electrical characteristics of single layer grids Scaling of on-chip power supply voltage drop Impedance characteristics of multi-layer grids Summary

Problem of Power Delivery
Objective: Deliver power to the load while maintaining the power supply voltages within target noise margins under specified load demands Obstacles: Power lines are not ideal and have finite resistance and inductance Resistive noise VR = IR Caused by high transient currents drawn by the load Inductive noise VL = L di/dt Caused by high current slew rates di/dt produced by the load

Moore's Law—Integrated Circuit Complexity Rapidly Increases

Clock Frequency Increases with Scaling

Power Consumption Increases with Rising Complexity and Speed

Power Current Increases Drastically with Technology Scaling

ITRS Forecast for Power Current Demands
Rate of increase in transient current is approximately double the increase in average current Due to the increase in clock frequency Agrees with ideal scaling analysis (S is the scaling factor) Average current per circuit area IA scales as S Transient current per circuit area dIA/dt scales as S2

Projections of Transient Current Demands in ICs
Current slew rate demands are rising faster than average current demands Inductive noise is increasing faster than resistive noise

Resource Requirements for On-Chip Power Distribution Networks
Average current and transient current demands of integrated circuits increase with technology scaling Power distribution networks use an increasingly larger share of on-chip resources to satisfy increasing demand Share of metal resources increases IBM Power4 CPU: 28% of on-chip metal Hewlett-Packard PA-8500: >35% of on-chip metal On-chip decoupling capacitors occupy significant area Typically 5% to 15% of chip area Optimizing the on-chip power distribution network can significantly increase the share of metal resources available for signal routing

Inductive Characteristics of Power Distribution Networks
Affects the integrity of the signals Primary current return path in on-chip single ended signals Return current flows through neighboring signal wires Causes signal-to-signal crosstalk Affects the integrity of the power supply Simultaneous switching noise RLC resonances within the power grid

Design of Power Distribution Grid Impedance Characteristics
Inductive characteristics of power distribution grids affect Efficient placement of decoupling capacitors Model of simultaneous switching noise [Vemuru, TAP’96], [Tang and Friedman, TVLSI’02] RLC analysis and verification of on-chip power distribution networks [Nassif and Kozhaya, ISCAS’00], [Bobba and Hajj, ISLPED’01], [Zheng and Tenhunen, TAP’01] Analysis of resonant behavior in on-chip power grids

Design Flow of Global Power Distribution Networks
VLSI Design Flow Power Grid Design Flow Resource allocation Pre-floorplan analysis (uniform current distribution is assumed) basic track topology, line width, pitch and layer allocation, I/O pad number, and location Floorplan-based analysis (uniform current distribution within blocks) block-specific line width and pitch Post-layout back annotation and analysis (based on worst case current waveforms) minor local adjustments of the grid Behavioral RTL Circuit Logic Layout Power grid tradeoff data Global power distribution networks are conservatively designed to satisfy worst case requirements

Physical Characteristics of P/G Networks

On-Chip Power Distribution Networks
Design of on-chip power distribution networks is constrained by several considerations Network impedance Metal resources Electromigration constraints Structure of on-chip power distribution network is often combination of several basic styles Routed Mesh Grid Planes

Routed Power Distribution Networks
Routed networks are typically used in low power circuits with limited interconnect resources Low area overhead Relatively low robustness Failure of single interconnect segment usually leads to circuit failure

Mesh Power Distribution Networks
Mesh networks are typically used in relatively low power circuits with limited interconnect resources Greater area overhead Improved robustness

Mesh Power Distribution Networks 3-D
Mesh networks are typically used in relatively low power circuits with limited interconnect resources Greater area overhead Improved robustness

Grid Power Distribution Networks
Grid networks are the preferred style in contemporary high power, high complexity circuits High area overhead Highly robust

Power Distribution Planes
Power and ground planes Power planes are used in high speed circuits where signal integrity is primary concern Greatest area overhead Superior impedance characteristics

Cascaded Power/Ground Rings
For ICs where pads are located along periphery Primary advantage: Signal routing at higher metal layers is possible

Power Distribution Planes
Power planes are used in high speed circuits where signal integrity is primary concern Greatest area overhead Superior impedance characteristics

Evolution of On-Chip Power Distribution Networks in Alpha Microprocessors
Alpha W, 39 A 0.18 mm, 7M flip-chip Alpha W, 9 A 0.75 mm, 3M Alpha W, 16 A 0.5 mm, 4M Alpha W, 33 A 0.35 mm, 6M Single layer grid Two layer grid Two power planes Power planes not required for power delivery but retained for data signal integrity Gronowski et al., High-Performance Microprocessor Design, JSSC, Vol. 33, No. 5, pp , May 1998.

Summary: Power Distribution Systems
Electrical behavior of a power distribution system is systematically described Controlling the resistance of the decoupling capacitors and interconnect is essential for efficient design of low impedance power distribution systems Maintaining adequate damping characteristics of chip-package resonance is particularly challenging On-chip capacitors should have a relatively high effective resistance Two-dimensional nature of package and on-chip networks This treatment provides basis for efficient management of resonant behavior in complex package and on-chip networks

VLSI Design Flow Power Grid Design Flow Resource allocation Pre-floorplan analysis (uniform current distribution is assumed) basic track topology, line width, pitch and layer allocation, I/O pad number, and location Floorplan-based analysis (uniform current distribution within blocks) block-specific line width and pitch Post-layout back annotation and analysis (based on worst case current waveforms) minor local adjustments of the grid Behavioral RTL Circuit Logic Layout Power grid tradeoff data Global power distribution networks are conservatively designed to satisfy worst case requirements 34

Pre-floorplan Stage Grid topology Location of power/ground pads
Width and pitch of power/ground metal layers Ad hoc assumptions to estimate on-chip current Information obtained from previous circuits is scaled

Post-Floorplan Stage Important intermediate stage
Majority of problems are detected and mitigated in this step Widen existing power lines Insert additional lines Increase on-chip decoupling capacitance Moderate complexity permits iterative analysis More accurate current estimation is achieved at this stage

Current Estimation

Post-Layout Stage Final stage, physical design is close to completion
Major modification to power network is extremely difficult Only minor changes can be tolerated Reason for overly conservative design at pre- and post-floorplan stages

Power Distribution Analysis
Global problem, current at one location can affect voltage at all other locations Entire power grid must be analyzed simultaneously If partitioned, can produce serious error Number of nodes in grid >> 25 million in large microprocessor Must also consider transistor currents Requires SPICE-like accuracy - infeasible Nonlinear simulation Linear Devices – assume constant VDD and GND – Partitioned into blocks and simulated in parallel Iterate with more accurate VDD and GND - May not converge Interconnect – RLC of power grid and transistor currents  time varying current sources Linear simulator across entire power distribution network (Voltage at all power grid tap points) Constant VDD and GND for transistors are primary problem to approach Conservative since overestimated currents

Typical 2-D Power Network Model

Static Analysis Characterize long term average IR drop along network
Based on average steady state current drawn from power supply Capacitances are assumed as open circuit Inductances are assumed as short circuit Complexity significantly lower than dynamic analysis Identifies weak spots Dynamic analysis is performed on weak spots Also useful to characterize electromigration reliability

Dynamic Analysis Type of transient analysis
Can observe temporal variation of power supply noise Capacitance and inductance need to be considered Time correlation of various circuit blocks can also be examined Complexity is significantly higher

Agenda Motivation On-chip power distribution networks Computer-aided design and analysis Electrical characteristics of single layer grids Grid types and general inductive properties Inductance variation on grid dimensions Inductance variation with frequency Inductance/resistance/area tradeoffs Scaling of on-chip power supply voltage drop Impedance characteristics of multi-layer grids Summary

General Power Transmission Circuit
Equivalent inductance diagram Forward inductance Lpp Return inductance Lgg Mutual inductive coupling Lpg

Inductance of Power Current Loop
Lloop = Lpp + Lgg – 2Lpg How to minimize loop inductance Lloop ? Minimize partial self inductance, Lpp and Lgg Maximize the partial inductance Lpg The mutual coupling

How to Minimize Lpp and Lgg ?
In general, the forward current and return current paths consist of several conductors in parallel I2 I1 Consider two parallel conductors Net inductance of a parallel circuit How to minimize the net parallel inductance L1||2 ? Minimize partial self inductance, L11 and L22 Minimize the coupling Partial mutual inductance L12

Parallel versus Antiparallel Currents
Strong coupling of antiparallel currents reduces the circuit inductance Strong coupling of parallel currents increases the circuit inductance I1 I2 Antiparallel currents I1 I2 Parallel currents Line separation determines the line coupling (per length) To minimize circuit inductance Parallel currents should be spatially separated from each other Antiparallel currents should be placed in close proximity

Three Power Grid Types Investigated
Non-interdigitated The power lines occupy one half of the grid, the ground lines occupy the other half Interdigitated Power and ground lines are interdigitated and uniformly distributed Paired Power and ground lines are placed in uniformly distributed power/ground line pairs

Cross Section of Non-interdigitated Grid
This configuration has a relatively high inductance Coupling of parallel currents is relatively strong Separation between parallel currents is equal to the line pitch P Coupling of antiparallel currents is relatively weak Separation between antiparallel currents is large Intuitively, equivalent to the width of the current loop On average, half of the grid width P Average width of the current loop How can this grid be improved to lower inductance? Interdigitate power and ground lines Spread lines over the entire width of the grid

Cross Section of Interdigitated Grid
Lower inductance as compared to non-interdigitated grids Coupling of parallel currents is relatively weak Separation between parallel currents is equal to 2P Stronger coupling of antiparallel currents Separation between antiparallel currents is equal to P Smaller effective width (and area) of the current loop P Effective width of the current loop 2P Can grid be further improved to lower inductance? Place the power and ground lines in close proximity to minimize the effective width of the current loop

Cross Section of Paired Grid
Lower inductance as compared to interdigitated grids Coupling of parallel currents is relatively weak Separation between parallel currents is equal to 2P Strong coupling of antiparallel currents Separation between antiparallel currents is the minimum spacing S0 Small effective width (and area) of the current loop 2P Effective width of the current loop S0 No further significant improvements?

Analysis Tools and Assumptions
FastHenry* is used to evaluate the grid inductance Magneto-quasistatic approximation Displacement currents through interconnect capacitances are ignored Accurate for power and ground lines Geometric and technology parameters Metal lines are 1 mm thick Metal resistivity is 1.72 mW·cm Within the resistance range reported for Cu interconnect Grid length is 1000 mm Minimum line width and spacing are 0.5 mm * M. Kamon, M. J. Tsuk, and J. White, "FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program," IEEE Transactions on Microwave Theory and Techniques, Vol. 42, No. 9, pp , September 1994

Dependence of Inductance on Grid Type
Frequency = 1 GHz Grid inductance depends on grid type Non-interdigitated grids have the largest inductance Interdigitated grids have intermediate inductance Paired grids have the lowest inductance Interdigitated grid, 1 mm  1 mm lines Paired grid, 1 mm  1 mm lines Non-interdigitated grid, 1 mm  1 mm lines

Dependence of Inductance on the Number of Lines in the Grid
Interdigitated grid, 1 mm  1 mm lines Paired grid, 1 mm  1 mm lines Non-interdigitated grid, 1 mm  1 mm lines Frequency = 1 GHz Inductance of non-interdigitated grids decreases slowly (slower than 1/N) with the number of lines N Inductance of paired and interdigitated grids decreases 1/N with the number of lines N Only the inductive coupling to the closest neighbors matters Due to periodic structure Coupling to distant lines cancels out Behaves as if inductive coupling is a short range phenomenon *A. V. Mezhiba and E. G. Friedman, Proc. of ISCAS, vol. I, pp , March 2002

Long distance coupling cancellation
Effective Range of Inductive Coupling Is Greatly Reduced in Power Grids Long distance coupling cancellation Long distance inductive coupling nearly cancels in power distribution grids with alternating power and ground lines Coupling to the distant power "aggressor" line is nearly canceled by coupling to the ground lines adjacent to the "aggressor" Only coupling to the nearest neighbors makes a significant contribution to the overall grid inductance Inductive coupling is effectively a local phenomenon in power distribution grids Assumes a balanced circuit Locally, the power line current is equal to the ground line current A. V. Mezhiba and E. G. Friedman, "Inductive Properties of High Performance Power Distribution Grids," IEEE Transactions on VLSI Systems, Vol. 10, No. 6, pp , December 2002

Inductance Estimation for Single Layer Grid
8 lines Practically exact N lines, N > 8 2 lines Overestimates by ~ 10% 4 lines Overestimates by ~ 5% Analytic analysis of only a small portion of the grid (two or four lines) provides a reasonably accurate estimate of the entire grid inductance L2 and L4 can be calculated analytically Allows efficient computation

Inductive Properties of Single Layer Grids
The same R and L Sheet resistance (Ohms per square) R Sheet inductance (Henrys per square) L Conveniently characterize the electrical properties of power grids Independent of grid dimensions The same height, width, and pitch Produce the same R and L *A. V. Mezhiba and E. G. Friedman, Proceedings of ISCAS, pp , March 2002

Dependence of Inductance on Frequency: Skin and Proximity Effects
Inductance of a conductor decreases with frequency due to several effects Although inductive impedance jwL increases with frequency f Skin effect Current concentrates at the surface of a conductor Internal inductance of the conductor decreases Current and magnetic field at the core of the conductor decrease Negligible effect on inductance in integrated circuits The drop in the internal inductance is negligibly small A fraction of the low frequency internal inductance, ~0.05 nH/mm Proximity effect Current concentrates on the conductor side closest to the current return path Significant only in adjacent wide wires carrying very high frequency signals High f Low f Low f High f Antiparallel currents Parallel currents

Dependence of Inductance on Frequency: Multi-path Current Redistribution
In a circuit with multiple return paths, the current return path is frequency dependent Low frequency — determined by the resistance of the paths High frequency — determined by the inductance of the paths High , R << jwL Forward current Return 1, low L1, high R1 Return 2, high L2, low R2 I0 I1 I2 Low , R  jwL This effect is the primary source of inductance variation with frequency in integrated circuits

Inductance Variation with Frequency in Non-Interdigitated Grids
Inductance variation with frequency increases with line width The frequency of the onset of inductance variation decreases with line width

Inductance Variation with Frequency in Interdigitated Grids
Inductance variation with frequency is moderate No multi-path current redistribution Inductance variation with frequency increases with line width Due to weak proximity effects

Inductance Variation with Frequency in Paired Grids
Inductance variation with frequency is more significant as compared to interdigitated grids Inductance variation with frequency increases with line width Due to significant proximity effects

Dependence of Inductance on Frequency: Interdigitated and Paired Grids
Proximity effect Current concentrates on the side of the line reducing the loop area Decrease in inductance at 100 GHz as compared to 1 GHz Relatively moderate decrease in inductance with frequency Resistance and inductance are uniformly distributed among the wires Low and high frequency current distributions are nearly the same Inductance decrease occurs only due to skin and proximity effects Less than 10% decrease under typical conditions Higher decrease in paired grids with wide wires is due to the onset of proximity effects between closely spaced wide wires A. V. Mezhiba and E. G. Friedman, "Frequency Characteristics of High Speed Power Distribution Networks," Analog Integrated Circuits and Signal Processing, Volume 35, Numbers 2/3, pp , May/June 2003

Decrease in Inductance with Frequency versus Width of Non-Interdigitated Grids
Current redistribution with frequency Low frequency Uniform current distribution among grid wires High frequency Current concentrates toward the grid center Inductance decreases due to multi-path current redistribution Current concentrates toward the grid center at high frequency Decrease in inductance with frequency increases with grid width Multi-path current redistribution increases with grid width

Many Narrow Lines or Few Wide Lines?
Resources dedicated to the power grid are limited Increasing the wire width reduces the wire density of the grid Inductance of a single line decreases with increasing wire width The current density decreases, slowly (sublinearly) decreasing the inductance Number of wires in the grid decreases with the wire width The fewer lines in parallel, the higher the net grid inductance Less space is wasted for line separation A tradeoff exists between the inductance and resistance of the grid Objective: Given the area allocated to the power grid, choose the line width and spacing that minimizes the power supply noise under transient and peak current requirements of the load.

First Tradeoff Scenario – Constant Area
Constant area ratio A scenario A is the fraction of the plane area occupied by the power routing Includes the line (metal) area Includes the minimum spacing S0 for line to line isolation P W S0 A tradeoff exists between the grid inductance and resistance Grid sheet resistance decreases with increasing line width The fraction of the grid area filled with metal increases Grid sheet inductance increases with increasing line width The decrease in the inductance of the wider lines is insufficient to make up for the reduced density of the lines Fewer parallel lines

Grid Inductance versus Line Width Under a Constant Area Ratio A
Grid width Larger frequency dependence of paired grid due to proximity effect Grid width increases with line width The number of lines in the grid does not change (ten lines) Line spacing increases with line width to keep area ratio A constant Inductance of the grids with different line widths can not be directly compared Sheet inductance: L =

Grid Sheet Inductance versus Line Width
Sheet inductance increases linearly with line width under a constant grid area ratio constraint A A is the fraction of the plane area dedicated to the power grid Includes both the metal area of the line and the minimum line spacing area Minimum line spacing is assumed to be constant at 0.5 mm Larger frequency dependence of paired grid due to proximity effect

Inductance vs. Resistance Tradeoffs
High DVR = IR Low DVL = L dI/dt Low DVR = IR High DVL = L dI/dt The area of the power grid area ratio A is maintained constant LR is the grid sheet inductance under a constant area constraint R A is the grid sheet resistance under a constant area constraint Optimum choice of wire width depends upon the I to dI/dt ratio *A. V. Mezhiba and E. G. Friedman, Proc. of ISCAS, vol. I, pp , March 2002

Second Tradeoff Scenario – Constant Resistance
Constant metal ratio M scenario M is the fraction of the plane area occupied by the power grid metal Includes the line (metal) area only Constant M is equivalent to constant sheet resistance of the grid R R = r/M, where r is the sheet resistance of the metalization layer P W A tradeoff exists between the grid inductance and area Grid area ratio A decreases with line width The fewer the lines, the fewer line spacings, the smaller area used for spacing Grid sheet inductance increases with line width The decrease in the inductance of the wider lines is insufficient to make up for the reduced line density

Grid Inductance versus Line Width Under a Constant Metal Ratio M
Grid width Larger frequency dependence of paired grid due to proximity effect Grid width increases with line width The number of lines in the grid does not change (ten lines) Line spacing increases with line width to keep metal ratio M constant Inductance of the grids with different line width can not be compared directly

Grid Sheet Inductance versus Line Width
Sheet inductance increases linearly with line width under a constant metal ratio M M is the fraction of the plane area filled with the power grid metal Only includes metal area of the lines Larger frequency dependence of paired grid due to proximity effect

Inductance vs. Area Tradeoffs in Power Distribution Grids
High area A Low DVL = L dI/dt Low area A High DVL = L dI/dt The metal ratio M of the power grid is maintained constant LR is the sheet inductance under a constant resistance constraint AR is the grid area ratio under a constant grid resistance constraint

Summary: Power Grid Inductance
Inductance of grids with alternating power and ground lines (i.e., paired and interdigitated) is lower than the inductance of non-interdigitated grids Inductance of interdigitated grids is more than twofold greater as compared to paired grids Inductance of grids with alternating power and ground lines (paired and interdigitated grids) Increases linearly with grid length Inversely proportional to the number of lines in the grid Relatively constant with frequency Sheet inductance is a convenient measure of the grid inductance

Summary: Inductance-Related Tradeoffs
Inductance versus resistance tradeoff exists under a constant grid area ratio constraint Sheet inductance increases linearly with line width Inductive L di/dt voltage drop increases with wire width Sheet resistance decreases with line width Resistive IR voltage drop decreases with wire width A minimum power supply noise (L di/dt + IR) exists Depends upon the transient and peak current demands of the load Inductance versus area tradeoff exists under a constant resistance constraint Grid area decreases with line width

Agenda Motivation On-chip power distribution networks Computer-aided design and analysis Electrical characteristics of single layer grids Scaling of on-chip power supply voltage drop Model of on-chip power voltage drop Scaling in a constant interconnect thickness scenario Scaling in a scaled interconnect thickness scenario Impedance characteristics of multi-layer grids Summary

Power Distribution in a Flip-Chip Package
Ground Each power/ground pad distributes current in the immediately adjacent area Referred to as a power cell

Model of the Resistive Voltage Drop*
Circular distribution area (power cell) of radius rc Uniform current per area IA Current is distributed from the pad with radius rp Effective sheet resistance of the power grid is r rc rp Resistive noise is proportional to the current of the power cell Icell and the sheet resistance of the power distribution network r *L. A. Arledge Jr. and W. T. Lynch, Proc. of Symp. On IC/Package Design Integration, 1998

Properties of Power Grid Inductance*
Inductance of power grids with interdigitating power and ground lines Increases linearly with grid length Inversely proportional to the number of lines in the grid Relatively constant with frequency Provided the width and pitch of the lines are maintained constant Power grid inductance behaves analogously to grid resistance Sheet inductance (Henrys per square) L is a convenient quantity to characterize the grid inductance Independent of the grid dimensions Analogous to the grid resistance r *A. V. Mezhiba and E. G. Friedman, Proc. of ISQED, pp , March 2002

Scaling Model of the Inductive Voltage Drop
Circular distribution area (power cell) of radius rc Uniform transient current per area dIA/dt Current is distributed from the pad of radius rp Effective sheet inductance of the power grid is r rc rp  Inductive noise is proportional to the transient current of the power cell dIcell/dt and the sheet inductance of the power distribution network L

Flip-Chip Pad Pitch Scaling
The rate of pad pitch P scaling is roughly half the rate of the line pitch scaling, i.e., 1/S 1/2 Power cell area Acell~P2 scales as (1/S1/2)2 = 1/S Average current per power cell scales as IAAcell ~ S ·1/S ~ 1 Transient current per power cell scales as dIA/dt ·Acell ~ S2·1/S ~ S

First Interconnect Scaling Scenario
Scaling by 4 Thickness of the top interconnect layers is maintained constant Sheet resistance of the grid remains constant Sheet inductance of the grid remains constant

First Scenario: Power Noise Scaling
Resistive voltage drop is maintained constant Inductive voltage drop increases as S Signal to noise ratio of the resistive and inductive noise, SNRR and SNRL, decreases A. V. Mezhiba and E. G. Friedman, “Scaling Trends of On-Chip Power Distribution Noise," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 4, pp. April 2004

Power Noise Case Study A simple model of the on-chip power distribution grid Square grid covering one power cell Line width, height, and separation are 1 m ITRS data on current per area Provides a conservative estimate of the ratio of the inductive noise to the resistive noise Lower inductance to resistance ratio than in a typical power grid Power and ground lines are narrow and adjacent to each other

Scaling Trends of Power Distribution Noise
Inductive noise becomes comparable to resistive noise as technology approaches nanometer range

Second Interconnect Scaling Scenario
Scaling by S Thickness of the top interconnect layers is scaled proportionally with the device features Sheet resistance of the grid increases by S Sheet inductance of the grid decreases by S

Scaling of Power Grid Inductance
Inductance per length of an interconnect structure is maintained constant with ideal scaling All dimensions are scaled uniformly Ratio of the cross-sectional dimensions are maintained constant Inductance is weakly dependent on the line aspect ratio Scaled by 2 Line density is doubled Sheet inductance is halved Sheet inductance decreases as 1/S Density of power lines (lines per mm) increases as S

Second Scenario: Power Noise Scaling
Resistive voltage drop increases as S Inductive voltage drop is maintained constant Signal to noise ratio of the resistive and inductive noise, SNRR and SNRL, decreases

Scaling Trends of Power Distribution Noise
Inductive noise decreases while resistive noise increases as compared to the first scenario Overall noise magnitude increases if the resistive noise is dominant

Summary: Scaling of On-Chip Power Voltage Drop
With dimensions of the top level interconnect maintained constant Resistive noise SNR scales as 1/S Inductive noise SNR scales as 1/S2 With dimensions of the top level interconnect scaled with device dimensions Resistive noise SNR scales as 1/S2 Inductive noise SNR scales as 1/S As technology approaches the nanometer range, careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary to achieve minimum power noise levels

Electrical Properties of Multi-Layer Grids
Power grids are comprised of two to four grid layers in the north-south and east-west directions Only affects inductance and resistance in north-south direction Only affects inductance and resistance in east-west direction

Grid Layers Typically Have Disparate Electrical Characteristics
Grid layers have different resistive and inductive characteristics Layers with smaller net cross-sectional area have higher resistance Layers with smaller line pitch have lower inductance Lower grid layers have smaller line width, height, and pitch Lower inductance and higher resistance Each layer can be modeled as a separate RL branch

Inductive Coupling between Grid Layers
= 0 Coupling is significant only under two necessary conditions The grid layers have the same line pitch The separation between grid layers is small as compared to the pitch Under these conditions, the overall inductance depends on the mutual alignment of the grid layers Alignment with minimum inductance Alignment with maximum inductance In practical grids, the coupling cancels

Impedance Characteristics of Comprising Grid Layers
The impedance properties of several grid layers can be modeled with several uncoupled parallel RL paths Above a certain knee frequency the impedance of a grid layer is dominated by the inductive reactance Impedance increases linearly with frequency The knee frequency is lower for the thicker upper metal layers Analytic expressions for the overall resistance and inductance have been developed * A. V. Mezhiba and E. G. Friedman, “Impedance Characteristics of Power Distribution Networks in Nanoscale Integrated Circuits,” IEEE Transactions on VLSI Systems, November 2004.

Model of On-Chip Power Distribution System
Low frequency current (low R) Up to 10 metal layers Middle frequency High frequency current (low L) Resistive R□ = R□1 | R□2 | R□3 Impedance of two metal parallel layers Inductive L□ = L□1 | L□2 | L□3 Model of on-chip power distribution grids Reduced complexity (shortened simulation time) Three layers (R, RL, and L) Highly accurate as compared to RL mesh (one layer) A. V. Mezhiba and E. G. Friedman, “Impedance Characteristics of Power Distribution Grids in Nanoscale Integrated Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 11, pp , November 2004

Impedance Characteristics of Multi-Layer Grids Vary with Frequency
Each layer serves as the lowest impedance path within a certain frequency range Carries the largest share of current Has the greatest impact on the overall impedance Grid inductance decreases with frequency Grid resistance increases with frequency Resistance and inductance can be analytically determined as a function of frequency

Two-Layer Grid Case Study
Two parallel grid layers with different electrical characteristics Upper layer — thick and wide lines Low resistance and high inductance Lower layer — thin and narrow lines High resistance and low inductance

Analysis Tools and Assumptions
FastHenry tool* is used to evaluate the grid inductance Magneto-quasistatic approximation Displacement currents through interconnect capacitances are ignored Accurate for power and ground lines Metal resistivity is 1.72 mW·cm Within the resistance range reported for Cu interconnect * M. Kamon, M. J. Tsuk, and J. White, "FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program," IEEE Transactions on Microwave Theory and Techniques, Vol. 42, No. 9, pp , September 1994

Variation of Inductance in Multi-Layer Grids
Significant multi-path current redistribution Low frequency impedance is dominated by the upper layer High frequency impedance is dominated by the lower layer L1<<L2 R1>>R2

Variation of Resistance in Multi-Layer Grids
Significant multi-path current redistribution Low frequency impedance is dominated by the upper layer High frequency impedance is dominated by the lower layer L1<<L2 R1>>R2 L1<<L2 R1>>R2

Variation of Impedance in Multi-Layer Grids
Impedance of a multi-layer grid is lower than the impedance of any comprising layer at all frequencies Multi-path current redistribution Current flows through the path of least impedance

Summary: Multi-Layer Grids
Inductance and resistance of multi-layer grids vary significantly with frequency Unlike the inductance and resistance of the individual grid layers Due to disparate electrical properties of comprising grid layers Significant current redistribution with frequency among grid layers Grid inductance and grid resistance become interdependent Resistance-only model underestimates resistance at high frequencies Inductance-only model underestimates inductance at low frequencies An analytic method has been developed to determine the inductive and resistive characteristics of a multi-layer grid from the electrical properties of the individual grid layers

VLSI Design Flow Power Grid Design Flow Present Work Resource allocation Pre-floorplan analysis (uniform current distribution is assumed) basic track topology, line width, pitch and layer allocation, I/O pad number and location Floorplan-based analysis (uniform current distribution within blocks) block-specific line width and pitch Post-layout back annotation and analysis (based on the worst case current waveforms) minor local adjustments of the grid Behavioral RTL Circuit Logic Layout Area/resistance/ inductance tradeoff data Resource and tradeoff information necessary for efficiently exploring the power distribution grid design space

Summary Increasing speed and current of integrated circuits necessitate rapid decrease in impedance of power distribution system over wide frequency range Hierarchical structure of decoupling capacitors is necessary to manage impedance of power distribution system over wide frequency range Controlling interconnect inductance is of primary importance in reducing high frequency impedance High frequency impedance characteristics can be controlled by adjusting structure of power distribution grids Multi-layer grids are well suited for maintaining low impedance power distribution network over wide range of frequencies

Possible Research Topics
Develop methodology for allocating on-chip decoupling capacitors in single and multi-voltage systems Explore inductance/resistance/area tradeoffs in on-chip power distribution grids Manage resources used by power distribution networks Efficiently estimate inductance of on-chip power grids Develop techniques to minimize power grid inductance Evaluate the impedance of multi-layer power grids

EE222_Lecture 5 On-Chip Power Distribution Network January 23, 2018

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