1. +5 +5 1 14 1
74LS00 3 IN
OUT 7 8 2
Gnd
Figure 1: (a) Logic Level Measurement (Measure voltage at OUT node).
(b) Power Supply Wiring.

2. Figure 2: Timing Characteristics (10%, 50%, 90% marked).
Out
fall t t PD
rise
Figure 2: Timing Characteristics (10%, 50%, 90% marked).

3. 1 2 3 4 5 6 13 12 11 10
Figure 3: Ring Oscillator (using a 74LS04).

4. +5 4 1 +5
1.8432 1 4 12
MHz 3 6 11 2 3
Xtal 2
CLK 5 13 10 8 9
GLITCH
Figure 4: Glitch Measurement Circuit (74LS00).

5. 11 10 9 8 +5 4 2 2A 2B 2C 2D 1
CLR1 13
1.8432
CLK2
CLR2
MHz 3
74LS393 2 12
Xtal
CLK1 1 1A 1B 1C 1D 3 4 5 6
Figure 5: Clock and Ripple Counter.

6. Figure 6: Synchronous Counter Wiring+5 +5 14 13 12 11 14 13 12 11 7 7 P Qa Qb Qc Qd P Qa Qb Qc Qd 10 15 10 15 T
RCO T
RCO 9 9 LD
74LS163 LD
74LS163 1 1
CLR
CLR A B C D A B C D 2 2 3 4 5 6 3 4 5 6
1.8432Mhz
Figure 6: Synchronous Counter Wiring

7. Figure 7: The first four digits on the seven-segment display

8. VDD
7-segment LCD
4.7K a f
VDD
YOUR b g
LOGIC
4.7K
HERE! e c d
dipswitch
Figure 8: Block diagram for testing your decoding logic