1. IntroductionLecture 1: Basic Ideas & Terminology
DIGITAL CONTROL SYSTEM
자동제어
PROF. KALYANA C. VELUVOLU (별루볼루 교수)
School of Electronics Engineering (전자공학부 IT 대학)

2. WEEK 8
Block Diagrams

3. DESIGN TECHNIQUES Topics: Digital Feedback Design
S-plane Method
z-plane Method
W-plane Method
Lead-lag Compensation

4. Three Design Approaches
S-plane Design: Design a continuous-time controller and then approximate it using a digital controller.
Advantage: Simple, tools readily available.
Disadvantages: Approximation errors, no guarantee on stability & performance after digital implementation.
z-plane Design: Design a digital controller directly for a digital system.
Advantages: No approx. errors, direct implementation.
Disadvantages: Design specifications need to be in the z-domain; Design tools need to be modified.
W-plane Design: Transform the digital system to the w-plane and apply continuous-time design methods
Advantages: No implementation errors, tools available
Disadvantages: Extra transformations.
Dr. Kalyana Veluvolu

5. DESIGN IN s-PLANE
Consider the unity feedback sampled-data system below
Dr. Kalyana Veluvolu

6. Use the first-order 𝑃𝑎𝑑𝑒 ′ approximation 𝑒 −𝑠𝑇 ≈ 1+(−𝑠𝑇/2) 1−(−𝑠𝑇/2) For the ZOH device, when T is small. 𝐺 𝑧𝑜 𝑠 = 1− 𝑒 −𝑠𝑇 𝑠 ≈ 2𝑇 𝑇𝑠+2 = 𝐺 𝑝𝑎 𝑠 Approximate model for sampler and ZOH 𝐺 𝐴 𝑠 = 1 𝑇 𝐺 𝑝𝑎 𝑠 = 2 𝑇𝑠+2
Dr. Kalyana Veluvolu

7. Dr. Kalyana Veluvolu

8. The design procedure is to first obtain a closed-loop model [ 𝐶 𝑠 𝑅 𝑠 ] 𝑇 for the approximate system: 𝐺_𝑃𝐶(𝑠)= 𝐺_𝐴(𝑠)𝐺_𝑥(𝑠)= 2 𝐾 𝑥 /𝑇 𝑠(𝑠+1)(𝑠+ 2 𝑇 ) So for T = 0.1 s, we get 𝐶(𝑠) 𝑅(𝑠) 𝑇 = 𝐺 𝑃𝐶 (𝑠) 1+ 𝐺 𝑃𝐶 (𝑠) = 20 𝐾 𝑥 𝑠 𝑠 2 +20𝑠+20 𝐾 𝑥 For this it is assumed that the desired value of 𝜁 for the dominant roots is This gives 𝐾 𝑥 =
Dr. Kalyana Veluvolu

9. Dr. Kalyana Veluvolu

10. Thus for a unit-step input, 𝐶(𝑠) 𝑇 = 9.543 𝑠 𝑠 3 +21 𝑠 2 +20𝑠+9.543
𝐶(𝑠) 𝑇 = 𝑠 𝑠 𝑠 2 +20𝑠+9.543
= 𝑠(𝑠 ±𝑗0.4883)(𝑠+20.03)
The step response is shown on the next slide.
Notice that the approximation error is virtually negligible. This is because T is very small. The cost is more computation. If T is larger, the ZOH unit may degrade the degree of stability. This can be compensated in two ways:
Modifying the gain
Inserting a compensator
Dr. Kalyana Veluvolu

11. Dr. Kalyana Veluvolu

12. DESIGN IN z-PLANE:
This is an exact approach, requiring the z-transfer function of the forward loop. For the same example, we have 𝐺 𝑧 =𝑍 𝐾 𝑥 (1− 𝑒 −𝑠𝑇 ) 𝑠 2 (𝑠+1)
= 1− 𝑧 −1 𝑍 𝐾 𝑥 𝑠 2 (𝑠+1)
= 𝐾 𝑧 𝑇−1+ 𝑒 −𝑇 𝑧+(1−𝑇 𝑒 −𝑇 − 𝑒 −𝑇 ) 𝑧 2 − 1− 𝑒 −𝑇 + 𝐾 𝑥 −𝑇 𝐾 𝑥 − 𝐾 𝑥 𝑒 −𝑇 𝑧+ 𝑒 −𝑇 + 𝐾 𝑥 − 𝐾 𝑥 (𝑇+1) 𝑒 −𝑇
Thus for T = 0.1 s,
𝐺 𝑧 𝑧 = 𝐾 𝑥 (𝑧 ) (𝑧−1)(𝑧−0.9048)
Dr. Kalyana Veluvolu

13. However, this technique requires the s-domain design specifications to be transformed into the z-domain. For our example, we may assume that we want the closed-loop system to have two dominant poles at (as in the previous design) 𝑠 1,2 =−0.4875±𝑗 Which correspond to 𝜁 = Translating these poles to the z-domain using 𝑧= 𝑒 𝑠𝑇 : 𝑧 1,2 =0.9513±𝑗 The control design can then be done using the root-locus technique (or other method like pole-placement & frequency domain design).
Dr. Kalyana Veluvolu

14. Root-locus diagram (Global):
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15. Root-locus diagram (for the region of interest):
The loop gain is determined to be 𝐾 𝑥 =0.478(similar as above)
Dr. Kalyana Veluvolu

16. DESIGN IN W-PLANE
In this method, the first step is the same as the z-plane method, i.e., to obtain the z-domain open open- loop transfer function: 𝐺 𝑧 𝑧 = 𝐾 𝑥 (𝑧 ) (𝑧−1)(𝑧−0.9048) Then, convert it to the w-plane using the Tustin transformation2: 𝑧= 𝑇𝑤+2 −𝑇𝑤+2 𝑤= 2 𝑇 𝑧−1 𝑧+1 For T = 0.1s, this gives 𝐺 𝑤 𝑤 = −4.1327× 10 −5 𝐾 𝑥 (𝑤−20)(𝑤+1200) 𝑤(𝑤 ) ≈ − 𝐾 𝑥 𝑤−20 𝑤 𝑤 (𝑤+1200)≈1200
Dr. Kalyana Veluvolu

17. Design specifications:
When T is small (as in our case), simply use the specifications in the s-plane on the w- plane. In our case, the closed-loop ploles should be
𝑤 1,2 ≈ 𝑠 1,2 =−0.4875±𝑗0.4883
When T is relatively large, the specifications in the s-plane need to be converted into the w-plane. For closed-loop poles, the conversion is done by
𝑤 𝑖 = 2 𝑇 𝑧 𝑖 −1 𝑧 𝑖 +1 = 2 𝑇 𝑒 𝑠 𝑖 𝑇 −1 𝑒 𝑠 𝑖 𝑇 +1
Dr. Kalyana Veluvolu

18. Root-locus Diagram (Global):
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19. Root-locus diagram (in the region of interest):
The required gain for is 𝐾 𝑥 =0.481 (again similar as above)
Dr. Kalyana Veluvolu

20. LEAD-LAG COMPENSATION
In the previous design examples, we only tuned the loop gain. In many applications, this is not sufficient to achieve satisfactory closed-loop performance. Lead-lag compensation allows the loop dynamics to be “shaped” in a desired way.
Consider the feedback control system as below;
𝐷 𝑐 𝑧 =𝐾 𝑧−𝑎 𝑧−𝑏 , −1<𝑎,𝑏<1
Phase lead: a>b
Phase lag: a<b
Dr. Kalyana Veluvolu

21. Use of lead-lag compensator:
Lag compensators are used to improve the steady state performance (reducing steady state errors). It should not alter the transient (or dynamic) performance of the system. For this purpose, the compensator is chosen to be: K = 1, a<b, but and b are both very close to 1 to give large steady state gain, i.e.
𝑧−𝑎 𝑧−𝑏 𝑧=1 ≫1
Lead compensator are used to improve the transient performance (affecting damping and rise time, improving stability). For this purpose, the pole and zero of the compensator are chosen to modify the root loci.
Lead-lag compensators can be designed using any of the three methods we discussed before.
Dr. Kalyana Veluvolu

22. Design using the s-plane First design a continuous-time lead-lag compensator 𝐷 𝑐 𝑠 =𝐾 𝑠+𝛼 𝑠+𝛽 , 𝛼,𝛽>0 Then map it to the z-domain using a bilinear transformation. Design using the w-plane First map the discrete-time open-loop transfer function to the w-plane. Design a lead-lag compensator 𝐷 𝑐 𝑤 =𝐾 𝑤+𝛼 𝑤+𝛽 , 𝛼,𝛽>0 Note: Bilinear transformation converts a lead (or lag) compensator to a lead (or lag) compensator. – Please verify it.
Dr. Kalyana Veluvolu

23. Example: Lead compensation for the design example as before
Example: Lead compensation for the design example as before. Use the s-plane method.
Recall the approximate continuous-time model is given by :
𝐺 𝑃𝐶 𝑠 = 𝐺 𝐴 𝑠 𝐺 𝑥 𝑠 = 2 𝐾 𝑥 /𝑇 𝑠(𝑠+1)(𝑠+2/𝑇) =20 𝐾 𝑥 /𝑠(𝑠+1)(𝑠+20)
To give the damping of 𝜁 = , the gain 𝐾 𝑥 = This gives 𝐾 𝑥 =4767. This gives 𝑠 1,2 = −0.4875±𝑗 and settling time = 8.6 sec.
In order to improve (reduce) the settling time, we need to shifty the closed-loop poles (hence the root loci) to the left (in the s-plane). This requires a lead compensator.
Choose
𝐷 𝑐 𝑠 =𝐾 𝑠+1 𝑠+10
Dr. Kalyana Veluvolu

24. Dr. Kalyana Veluvolu

25. Finally, we convert the controller to the z-domain using Tustin transformation for T = 0.1s. This gives 𝐷 𝑐 𝑧 = 47.15(𝑧−0.9048) 𝑧− The closed-loop system is given by 𝐶(𝑧) 𝑅(𝑧) = (𝑧 ) (𝑧−0.6104±𝑗0.2638) We see that the closed-loop poles are greatly improved.
Dr. Kalyana Veluvolu

26. 𝐷 𝑐 𝑧 𝐺 𝑧 𝑧 = 0.048 𝐾 𝑥 𝐾(𝑧+0.9672) (𝑧−1)(𝑧−0.3333)
Example: Lead compensation design using the z-plane. Lead-lag compensators can be designed directly using the root-locus diagram,.
Recall the distance-time open-loop transfer function:
𝐺 𝑧 𝑧 = 𝐾 𝑥 (𝑧 ) (𝑧−1)(𝑧−0.9048)
The idea of lead compensation here is to “move ” the open-loop pole at towards the origin so the root-loci will be shifted away from the unit circle. To this end, we simply choose
𝐷 𝑐 𝑧 = 𝐾(𝑧−0.9048) (𝑧−0.3333)
This gives
𝐷 𝑐 𝑧 𝐺 𝑧 𝑧 = 𝐾 𝑥 𝐾(𝑧 ) (𝑧−1)(𝑧−0.3333)
Dr. Kalyana Veluvolu

27. Dr. Kalyana Veluvolu

28. 𝑒 ∗ ∞ = lim 𝑡→∞ 𝑒 ∗ 𝑡 = lim 𝑤→0 𝑤𝑅(𝑤) 1+ 𝐺 𝑤 (𝑤) =0
Example: Lag compensation design using the w-plane method.
Recall the w-domain model:
𝐺 𝑤 𝑤 ≈ − 𝐾 𝑥 (𝑤−20) 𝑤(𝑤 )
Where 𝐾 𝑥 = The steady state error of the system can be readily determined by the final value theorem.
For a unit-step input, its w-domain representation is similar to the Laplace transform, i.e.,
𝑅(𝑤)≈ 1 𝑤
The steady state error is given by
𝑒 ∗ ∞ = lim 𝑡→∞ 𝑒 ∗ 𝑡 = lim 𝑤→0 𝑤𝑅(𝑤) 1+ 𝐺 𝑤 (𝑤) =0
Dr. Kalyana Veluvolu

29. Similarly, for a unit –ramp input, the w-domain representation is given by 𝑅 𝑤 = 1 𝑤 2 The steady state error is given by 𝑒 ∗ ∞ = lim 𝑤→0 𝑤𝑅(𝑤) 1+ 𝐺 𝑤 (𝑤) ≈2 We may reduce the steady –state error by increasing 𝐾 𝑥 but this will decrease the damping and cause too much overshoot or even instability. The alternative is to use a lag compensator.
Dr. Kalyana Veluvolu

30. Lag compensator: 𝐷 𝑐 𝑤 = 𝑤+0. 01 𝑤+0
Lag compensator: 𝐷 𝑐 𝑤 = 𝑤+0.01 𝑤 The loop transfer function is given by 𝐷 𝑐 (𝑤) 𝐺 𝑤 (𝑤)≈ − 𝐾 𝑥 (𝑤−20)(𝑤+0.01) 𝑤(𝑤 )(𝑤+0.001) The root-locus diagram is virtually unchanged at the region of dominant poles 𝑤 1,2 see diagram on next slide . However, the steady state error for thr ramp input is 10 times smaller because 𝐷 𝑐 0 = 10
Dr. Kalyana Veluvolu

31. Dr. Kalyana Veluvolu