1. Prof. Wahied Gharieb Ali Abdelaal Faculty of Engineering Computer and Systems Engineering Department Master and Diploma Students CSE 502: Control Systems (1) Topic# 9 Digital Control Design (PID)

2. 2 Outline  Introduction  Indirect Control Design  Digital PID control design  Design Examples  Direct Control Design  Direct Design using Root Locus  Deadbeat Control Design

3. 3 Introduction

4. 4 Indirect control Design

5. 5 Indirect Control Design

6. 6

7. 7 Approximations to Integration Indirect Control Design

8. 8 Euler’s Approximation Indirect Control Design

9. 9

10. 10 Indirect Control Design

11. 11 Indirect Control Design

12. 12 Indirect Control Design

13. 13 Indirect Control Design

14. 14 Indirect Control Design

15. 15 Digital PID Control Design  A proportional controller (P) reduces error responses to disturbances, but still allows a steady-state error.  When the controller includes a term proportional to the integral of the error (I), then the steady state error to a constant input is eliminated, although typically at the cost of deterioration in the dynamic response.  A derivative control typically makes the system better damped and more stable. Controller Effects

16. 16 Digital PID Control Design Rise timeMaximum overshoot Settling time Steady- state error PDecreaseIncreaseSmall change Decrease I Increase Eliminate DSmall change Decrease Small change  Note that these correlations may not be exactly accurate, because P, I and D gains are dependent of each other. Closed-loop Response

17. 17 Digital PID Control Design

18. 18 Digital PID Control Design PID controller with integral anti-windup

19. 19 Digital PID Control Design

20. 20 Digital PID Control Design

21. 21 Digital PID Control Design

22. 22 Digital PID Control Design

23. 23 Digital PID Control Design

24. 24 Digital PID Control Design

25. 25 Digital PID Control Design

26. 26 Discrete time equivalent of analog controller using Euler’s forward method (sampling period =T) Example Design Examples

27. 27 Discrete-time controllers when T = 0.4 s, which is relatively large as compared to the continuous-time controller’s fastest mode e−2t, the discrete-time controller approximation deviates significantly from the continuous-time controller. As the sampling interval is decreased, the step responses of the analog and discrete-time controllers are the same. Design Examples

28. 28 If we use the trapezoidal method, the transfer function of the digital controller becomes Design Examples

29. 29 Design Examples

30. 30 Design Examples

31. 31 Design Examples

32. 32 Design Examples

33. 33 Design Examples

34. 34 Design Examples

35. 35 Design Examples

36. 36 Design Examples

37. 37 Design Examples

38. 38 Design Examples

39. 39 Design Examples

40. 40 Design Examples

41. 41 Design Examples

42. 42 Design Examples

43. 43 Design Examples

44. 44 Direct Control Design

45. 45 Direct Control Design

46. 46 Direct Design using Root Locus

47. 47 Direct Design using Root Locus

48. 48 Direct Design using Root Locus

49. 49 Direct Design using Root Locus

50. 50 Direct Design using Root Locus

51. 51 Direct Design using Root Locus

52. 52 Direct Design using Root Locus

53. 53 Direct Design using Root Locus

54. 54 Direct Design using Root Locus

55. 55 Direct Design using Root Locus

56. 56 Direct Design using Root Locus N= Number of samples per oscillation

57. 57 Direct Design using Root Locus

58. 58 Deadbeat Control Design One difference between a continuous-data control system and a discrete-data control system is that the latter is capable of exhibiting a deadbeat response. A deadbeat response is one that reaches the desired reference trajectory in a minimum amount of time without error. In contrast, a continuous-data system reaches the final steady- state trajectory or value theoretically only when time reaches infinity. The switching operation of sampling allows the discrete-data systems to have a finite transient period.. The output response reaches the desired steady state with zero error in a minimum number of sampling periods without inter sampling oscillations. Design with Deadbeat Response

59. 59 Deadbeat Control Design For the sampled system with ZOH

60. 60 Example: Consider the forward-path transfer function of the uncompensated system is given by Deadbeat Control Design

61. 61 Deadbeat Control Design Closed loop poles at the origin, so it is so fast Steady state after two samples without error

62. 62 Deadbeat Control Design

63. 63 Deadbeat Control Design

64. 64 Deadbeat Control Design The output is delayed one sample than the input Explain

65. 65 Deadbeat Control Design

66. 66 Deadbeat Control Design

67. 67 Deadbeat Control Design

68. 68 Deadbeat Control Design

69. 69 Deadbeat Control Design

70. 70 Deadbeat Control Design

71. 71 Deadbeat Control Design

72. 72 Deadbeat Control Design

73. 73 Deadbeat Control Design

74. 74 Deadbeat Control Design

75. 75 Deadbeat Control Design