1. Alan Mishchenko Department of EECS UC Berkeley
Research Update
Alan Mishchenko
Department of EECS
UC Berkeley

2. Overview SAT-based synthesis in general
Remapping of standard cells for area
Fact extract and division algorithms
Improved SAT sweeping
Scaling synthesis to millions of nodes 2

3. SAT-based synthesis in general
Several flavors of SAT-based synthesis
“Exact minimum circuit” synthesis
Don’t-care-based synthesis
Structural synthesis

4. Remapping of standard cells for area
This is related to a new SAT-based synthesis project started a year ago
The main idea is to represent the care-set of a node as a circuit and use it in the SAT solver as a constrain
Results are encouraging

5. Fact extract and division algorithms
A new implementation of “fast_extract” has been developed, which has a linear complexity in terms of cubes (rather than quadratic)
The main idea is to use a hash-table to find shared divisors (rather than cube-pair enumeration)
Results are good
The same quality but improved runtime for large test-cases

6. Improved SAT sweeping
SAT sweeping is important in synthesis and verification
Not only for netlist reduction, but also for choice computation
Difficulty is how to combine SAT and simulation
The new idea is to perform SAT and simulation in a wave-front manner
Update wave-front with new sim patterns
Incrementally simulation while moving wave-front by one node
May be combined with several custom SAT features
Should be faster and more scalable

7. Scaling synthesis to millions of nodes
Scalability is a moving target
“How long it will take you to synthesize/map 1B AIG nodes?”
Partitioning can be used, but why partition with single-threaded implementation can be made faster
Basically, need to rethink all algorithms from the point of view of their “scalability for 1B AIG nodes”

8. Additional Slides

9. Constructing Boolean Relation Characterizing Node Functionality1
Construction steps:
Collect candidate divisors di of node n
Divisors are not in the TFO of n
Their support is a subset of that of node n
Duplicate the window of node n
Use the same set of input variables
Use a different set of output variables
Add inverter for node n in one copy
Create comparator for the outputs
Set the comparator to 1
This is the care set of node n
Convert all gates to CNF … d2 n n d1
How the relation is used:
Function n = F(d1, d2, …) belongs to the relation iff n can be implemented as a gate with function F in terms of divisors d1, d2, …
SAT solver is used to derive different functions F that can be used at the node X

10. CNF / Mapping Terminology
CNF is composed of variables, literals, and clauses
Each variable represents some aspect of the problem
Each literal is a variable in positive or negative polarity
Each clause is a disjunction of literals
CNF is a conjunction of clauses
Mapping is a set of gates completely covering the subject graph
Internal nodes of the subject graph can be
Used in the mapping (if mapping includes a gate rooted in this node)
Not used in the mapping (otherwise)
Gate cover represents a valid mapping if
Internal nodes driving the circuit outputs are used in the mapping
For each gate, its inputs are used in the mapping or are primary inputs

11. CNF for Structural Mapping
Disclaimer! This is a simplified formulation of standard-cell mapping
assumes one variable per node (rather than two variables for each polarity)
CNF variables
one variable (ni) for each node
ni is 1, iff node i is used in the mapping
one variable (cik) for each match (cut + gate) of the node
cik is 1, iff match k is used to map node I
CNF clauses
ni  k (cik) (If a node is used, one of its matches is used)
cik  f (nf) (If a match is used, all cut fanins are used)
o (no) (The nodes driving the outputs are used in the mapping)
i ni ≤ Limit (The gate count does not exceed the known mapping)