1. Applications of Distributed Arithmetic to Digital Signal Processing:
A Tutorial Review
Ref: Stanley A. White, “Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review,” IEEE ASSP Magazine, July, 1989

2. Outline: Distributed Arithmetic (DA) Introduction
Technical overview of DA
Increasing the speed of DA multiplication
Application of DA to a biquadratic digital filter
Conclusions

3. Distributed Arithmetic (DA, 1974) Introduction
The most-often encountered form of computation in DSP:
Sum of product
Dot-product
Inner-product
Executed most efficiently by DA
By careful design one may reduce gate count in a signal processing arithmetic unit by a number seldom smaller then 50% and often as large as 80%

4. Technical overview of DA
Advantage of DA: efficiency of mechanization
A frequently argued:
slowness because of its inherent bit-serial nature (not true)
Some modifications to increase the speed by employing techniques:
Plus more arithmetic operations
expense of exponentially increased memory

5. Technique overview -continued I
The sum of product:
where xk is a 2’s-complement binary number scaled such that | xk |<1 Ak is fixed coefficients
xk : {bk0, bk1, bk2……, bk(N-1) } , word length=N
where bk0 is the sign bit
Express each xk as:
(2)代入(1) =>
(1)
(2)
(3)

6. Technique overview -continued II
Critical step
where K=No. of taps (inputs), N: Wordlength of Data
(3)
(4)

7. Technique overview -continued III
Consider the equation (4)
has only 2K possible values
We can store it in a lookup-table(ROM): size=2*2K

8. Technique overview -continued IV
Example
Let no. of taps K=4
and the fixed coefficients are A1=0.72, A2=-0.3, A3=0.95, A4=0.11
We need 22K = 32-word ROM (k=4)

9. Example
Unfolding

10. Example -continued I
Hardware architecture

11. Example -continued II
Shorten the table
eq. (4)
(5)

12. Example -continued II Hardware architecture
Only 16 words of ROM are required,now.

13. Technique overview -advanced
Input
(6)
2‘s-complement
(7)

14. Technique overview -advanced I代入
Where and

15. Technique overview -advanced II
Hardware architecture

16. Increase the speed of DA multiplication
The way I:
Plus more arithmetic operations
Initial condition
Even part
Odd part

17. Increase the speed of DA multiplication
Hardware architecture of way I at the expense of linearly increased memory & arithmetic operation
Odd part(sign}
Even part
Initial
Condition
1/2*Q(0)

18. Increase the speed of DA multiplication
The way II: at the expense of exponentially increased memory
ROM : 2*7 words => 1*128 words
Hardware architecture

19. Application of DA to a biquadratic digital filter
Transfer function of a typical biquadratic digital filter:
The time-domain description:

20. Application of DA to a biquadratic digital filter
Hardware architecture

21. Application of DA to a biquadratic digital filter
The vector matrix equation
The relationships between two equations

22. Application of DA to a biquadratic digital filter
Normal form biquadratic filter

23. Application of DA to a biquadratic digital filter
DA realization

24. Application of DA to a biquadratic digital filter
Increase speed
1*3 BAAT DA structure
4*3 BAAT DA structure

25. Application of DA to a biquadratic digital filter
Increase speed II
2048 word/ROM
require 4 ROM
4 operations

26. Application of DA to a biquadratic digital filter
Increase speed III
32 word/ROM
require 8 ROM
8 operations

27. Conclusions
DA is a very efficient means to mechanize computations that are dominated by inner products
If performance/cost ratio is critical, DA should be seriously considered as a contender
When a many computing methods are compared, DA should be considered. It is not always (but often) best, and never poorly.