1. Applications Issues

2. Applications Issues: Powering up the HDMI Tx
When Hot-Plug Detect (HPD) is low the HDMI Tx will automatically go into power down mode.
After an HPD interrupt, register 0x41[6] must be set to ‘0’ to power up the part
During power down all registers except for 0x97 – 0xAF are reset to defaults
Most HDMI Tx devices (except AD9889, AD9389, AD9387, ADV7520, ADV7521) have an "HPD Override" function
These devices will operate same as if HPD = 1 when HPD "override" is enabled
On the ADV7510, the registers will reset on an HPD = 1 -> 0 transition
On the rest of these HDMI Tx devices the registers will not reset on an HPD = 1 -> 0 transition
HPD state and interrupt registers remain available even if HPD Override is enabled

3. Applications Issues: Clock Delay Adjustment
When input data to clock skew is not ideal, the clock delay can be adjusted in the HDMI Tx
For ADV7520 and later DDR falling edge can be adjusted independently
Delay
Register 0xBA[7:5]
-1200 ps
000
-800 ps
001
-400 ps
010
No Delay
011
400 ps
100
800 ps
101
1200 ps
110
Inverted
111

4. Applications Issues: EDID reading wait time
To ensure that the EDID/HDCP controller has sufficient time to read the EDID from the sink, the system software should wait a certain amount of time before judging that there is no EDID
The time recommended is based on 256 byte of DDC bus reading at 20KHz clock rate
This gives the minimum recommended time out period of
256 bytes x 10 cycle per byte x 50us = 128ms
To make system more robust, 0.5s is recommended to allow at least 3 EDID reading tries.

5. Applications Issues: High Speed I2C Bus
ADV7523 and later support 400kHz I2C operation.
ADV7511, ADV7523A, ADV7524A, ADV7525, ADV7541
Register 0xE6[1] must be set to 0
If 0xE6[1] is not set interrupt registers and mask registers are not reliable
All earlier Tx only support up to 100kHz I2C
AD9x89, AD9387, ADV7510, ADV7520, ADV7521

6. Common Apps Issues - HDCP
HDMI Tx contains a robust HDCP controller
Most HDCP timing is handled internally
All devices pass the official HDCP compliance test
Common Causes for HDCP problem
Ri Mismatch
Problem with HDCP keys
Some Tx need the internal key selected by a register setting
Some Tx need an external EEPROM
Vsync not stable
I2C NACK
Problem with DDC line capacitance
Extremely Long Cable

7. Common Apps Issues – Debugging HDCP
Make sure PLL locked register is always 1
Try probing the Vsync, DE, and Hsync inputs to the HDMI Tx
Are there any glitches?
A glitch would cause the mask on the Tx and Rx to mismatch
HDCP “snow” would result until the Ri mismatch causes reauthentication
If using AD9389B or ADV7520 make sure 0xBA[4] is set to 1.
If HDCP problems still exist probe the DDC lines to find exactly where the problem is
Scope with I2C software
Beagle I2C Analyzer

8. Common Apps Issues – Video Input Formatting
Requires communication between customer HW and SW engineers
Many pin connection options are available
Options for Hsync, Vsync, and DE input are available
Separate Hsync, Vsync, and DE
Embedded Syncs
Hsync and Vsync only
Requires an understanding of the part feeding the video’s format specification
Many chips output a format that will work with an encoder but requires special handling for HDMI

9. Quick Check for Input formatting problems
PLL Status Register
Check several times continuously
If PLL is not locked check the signal integrity of the video clock and R_EXT noise
Input VIC Detected Register
If a CEA861 format is used the VIC code should be available
If “0” is present, then the input format is not recognized

10. PLL Lock Issues A common issue is PLL not locking
This can be verified by checking register 0x9E[4]
Until 0x9E[4] = 1, focus on hardware
Generally there are 2 causes
Ringing on the CLK input
Low frequency noise near the R_EXT resistor
Solutions
Make sure all fixed register settings match recommendations
Add 100ohm serial resistor near the clock source
Reduce drive strength on the clock
Check layout for DDC lines or other low speed lines crossing the R_EXT traces

11. If customer is using a 480i format
480i input
If customer is using a 480i format
Best option is to have EAV and SAV timing matching the diagram on left
ADV752x and ADV7510 have flexible timing options allowing conversion to CEA 861
line no F V
525 1 22 21
Valid Video Area field 1
240
262
261 23
284
286
Valid Video Area field 2
263
524

12. Common Apps Issues – Audio Input Formatting
Low power Tx use SPDIF or I2S
AD9889B does not support 32 clock per fs format I2S
4 different formats are supported on the I2S pins
Compressed Audio
Compressed audio is passed as is through the Tx
No processing Done
Channel Status must be included
Dolby 5.1, DTS, Dolby Plus and DTS HRA are the same from HDMI Tx perspective
SPDIF is the easiest method for sending compressed audio
Special I2S mode with embedded channel status can also be used

13. Common Apps Issues – Audio Input Formatting
ADV7510 and ADV7511 Support High Bit Rate Audio
Compressed streams over 6.144mbs
Dolby True HD and DTS Master are the popular formats
These look the same from the HDMI Tx perspective
Input
Always uses the I2S lines
Can use I2S style or SPDIF style input
For inputs besides ADI Rx subpacket mapping may need to be modified