1. Course Webpage：swjx.scu.edu.cn/moodle
Operating System
Chapter01 Computer System Overview
四川大学软件学院 陈文
Course Webpage：swjx.scu.edu.cn/moodle
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2. Chapter01 Computer System Overview
1.1 Basic Elements(基本构成)
1.2 Run Instruction
1.3 interrupt
1.4 structure of storage
1.5 cache
1.6 I/O

3. 1.1 Basic Elements(1/3)

4. 1.1 Basic Elements(2/3)

5. 1.1 Basic Elements(3/4) CPU 总线 内存 程序 数据 寄存器组 寄存 地 程序计数器 地址总线 AB 址 译 码状态
寄存器
地址总线 AB 程序 数据
数据总线 DB
控制总线 CB 地 址 译 码 器
、、、
指令1
指令2
指令3
指令4
数据1
数据2
数据3
指令寄存器
数据暂存器
控制电路
指令译码器 寄存
程序计数器 R1 R2 R3 R4
寄存器组 运 算 IR PC

6. Chapter01 Computer System Overview
1.1 Basic Elements(基本构成)
1.2 Run Instruction(指令执行)
1.3 interrupt
1.3 structure of storage
1.5 cache
1.6 I/O

7. 1.2 Run Instruction (1/5)

8. 1.2 Run Instruction (2/5)

9. 1.2 Run Instruction (3/5)
指令1
指令2
指令3
前4位为操作码:

10. Chapter01 Computer System Overview
1.1 Basic Elements(基本构成)
1.2 Run Instruction(指令执行)
1.3 interrupt(中断)
1.4 structure of storage
1.5 cache
1.6 I/O

11. 1.3 Interrupt Introduction (1/2)
What the word of “interrupt” means?
E.g.: 你打断两个的对话，因为要问路
E.g.: 老师正在上课，手机突然叫了
E.g.: …

12. 1.3 Interrupt Introduction (2/2)
Why Interrupt in CS?
Most I/O devices are slower than the processor
Processor must pause to wait for device
E.g.: printer

13. 1.3.1 Examples of Interrupt (1/7)
Program 1
Instruction 1
Instruction n
data 1
data n M
WRITE1 PC IR R
CPU
WRITE1子程序
初始化I/O controler
完成要打印数据的Output
等待打印机完成打印
其他收尾工作
I/O controler
printer

14. 1.3.1 Examples of Interrupt (2/7)

15. 1.3.1 Examples of Interrupt (3/7)
Now, let add Interrupt into this example. So that
CPU can process other instructions, while printer can do its printing jobs
Concurrent: 并发
When the printer finished, it interrupts CPU

16. 1.3.1 Examples of Interrupt (4/7)
Program 1
Instruction 1
Instruction n
data 1
data n M
WRITE2 ？ PC IR R
CPU
WRITE2子程序
初始化I/O controler
完成要打印数据的Output
I/O controler
printer

17. 1.3.1 Examples of Interrupt (5/7)
CPU PC IR R
Program 1
Instruction 1
Instruction n
data 1
data n M
WRITE2
I/O controler
printer
WRITE2子程序
初始化I/O controler
完成要打印数据的Output
Instructions
Printer的中断服务程序
= Interrupt Handler
= Interrupt Service Routine

18. 1.3.1 Examples of Interrupt (6/7)
中断点
中断点

19. 1.3.1 Examples of Interrupt (7/7)
Timing Diagram Based on Long I/O Wait
1.3.5 Multiprogramming

20. 1.3.2 Interrupt Definition (1/3)
A mechanism by which other modules (I/O, memory) may interrupt the normal sequencing of the processor.
An I/O device can stop what the CPU is operating to provide some necessary service.

21. 1.3.2 Interrupt Definition (2/3)
Features of Interrupt
Unpredictable (不可预测性/随机性)
can be disable (可屏蔽性)
Can be nested (可嵌套性) ….

22. 1.3.2 Interrupt Definition (3/3)

23. 1.3.3 Interrupt Processing (1/8)
Suspends the normal sequence of execution

24. 1.3.3 Interrupt Processing (2/8)
Instruction 1
WRITE2
Program 1
Instruction n PC
Printer的中断服务程序
= Interrupt Handler
= Interrupt Service Routine IR
data 1
data n R
Instructions
CPU M
WRITE2子程序
初始化I/O controler
完成要打印数据的Output
I/O controler
printer

25. 1.3.3 Interrupt Processing (3/8)

26. 1.3.3 Interrupt Processing (4/8)

27. 1.3.3 Interrupt Processing (5/8)
修改PC的值成中断服务程序首指令的地址

28. 1.3.3 Interrupt Processing (6/8)
Interrupt Cycle
Processor checks for interrupts
If no interrupts fetch the next instruction for the current program
If an interrupt is pending, suspend execution of the current program, and execute the interrupt-handler routine

29. 1.3.3 Interrupt Processing (7/8)

30. 1.3.3 Interrupt Processing (8/8)

31. 1.3.4 Multiple Interrupts (1/4)
Q: What will happen if an I/O modules rouse a Interrupt, while the CPU is processing instruction of an ISR(interrupt service routine,中断服务例程)
That is interrupt an ISR

32. 1.3.4 Multiple Interrupts (2/4)
Method 1：Disable interrupts while an interrupt is being processed

33. 1.3.4 Multiple Interrupts (3/4)
Method 2： Define priorities for interrupts

34. 1.3.4 Multiple Interrupts (4/4)
An Example of Method 2

35. 1.3.5 Multiprogramming (1/2) Multiprogramming(多道程序)
Processor has more than one program to execute
The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O
After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt
More detail later

36. 1.3.5 Multiprogramming (2/2) printer Instruction 1 WRITE2 Program 1
Instruction n
data 1
Printer的中断服务程序 PC
data n IR
Instructions R
Instruction 1
Program 2
Instruction n
CPU M
I/O controler
printer

37. Chapter01 Computer System Overview
1.1 Basic Elements(基本构成)
1.2 Run Instruction(指令执行)
1.3 interrupt(中断)
1.4 structure of storage(存储结构)
1.5 cache
1.6 I/O

38. 1.4 The Memory Hierarchy (1/10)
The design constraints of a computer’s memory
How much : Capacity : larger
How fast : Speed : faster/ as fast as CPU
How expensive : Price : cheaper
CPU M
Disk

39. 1.4 The Memory Hierarchy (2/10)
(Speed , Price, Capacity)的不可兼得性/矛盾:
Faster access time, greater cost per bit
Greater capacity, smaller cost per bit
Greater capacity, slower access speed
What can we do?
中庸？
To use them all in the right way: Memory Hierarchy

40. 1.4 The Memory Hierarchy (3/10)
Memory Hierarchy： Three Levels

41. 1.4 The Memory Hierarchy (4/10)
Level 1：R ＋ Cache ＋ Main Memory
Semiconductor(半导体)
volatile (易失)
Bytes/words

42. 1.4 The Memory Hierarchy (5/10)
Level 2：
Auxiliary memory(辅助存储)
Nonvolatile(非易失)
files

43. 1.4 The Memory Hierarchy (6/10)
Level 3：many types
Tapes
…..

44. 1.4 The Memory Hierarchy (8/10)
Going Down the Hierarchy
Increasing capacity
Increasing access time ( that is slow speed )
Decreasing cost per bit
Decreasing frequency of access of the memory by the processor

45. 1.4 The Memory Hierarchy (9/10)
Decreasing frequency of access
Smaller, more expensive, faster memories are supplemented (补充) by larger, cheaper, slower memories
Smaller, more expensive, faster memories cache larger, cheaper, slower memories
Locality of reference(访问局部性/局部性原理/principle of locality)
What is it
Why it exists

46. 1.4 The Memory Hierarchy (10/10)
Hit ratio
Miss ratio
Average access time
Ts = H×Tn + (1-H)×(Tn + Tn+1)
CPU
Level n+1
Level n
0.1us
1us

47. Chapter01 Computer System Overview
1.1 Basic Elements(基本构成)
1.2 Run Instruction(指令执行)
1.3 interrupt(中断)
1.4 structure of storage(存储结构)
1.5 cache(高速缓存)
1.6 I/O

48. 1.5 Cache Memory (1/9) Its relationship with OS
It is a piece of hardware, which is invisible to OS
But, many of the principles used in Cache are similar to those of MM, which is a core modules of OS

49. 1.5 Cache Memory (2/9) Instruction Cycle and Memory Access
Processor speed is faster than memory speed
Increase the speed of memory
Exploit the principle of locality
Add something Between CPU and Memroy

50. 1.5 Cache Memory (3/9)

51. 1.5 Cache Memory (4/9) Cache Principles
Contains a copy of a portion of main memory
Processor first checks cache
(Hit) If not found, just use it. And do not need access to the memory
(Miss) If not found in cache, the block of memory containing the needed information is moved to the cache and delivered to the processor

52. 1.5 Cache Memory (5/9)

53. 1.5 Cache Memory (6/9)
术语：
Block
Slot/ Cache Line

54. 1.5 Cache Memory (7/9) Cache size Block size
Small caches have a significant impact on performance
Block size
The unit of data exchanged between cache and main memory
Larger block size more hits until probability of using newly fetched data becomes less than the probability of reusing data that have to be moved out of cache

55. 1.5 Cache Memory (8/9) Mapping function Replacement algorithm
Determines which cache location the block will occupy
Replacement algorithm
Determines which block to replace
Least-Recently-Used (LRU) algorithm

56. 1.5 Cache Memory (9/9) Write policy
When the memory write operation takes place
Two Methods
1) Can occur every time block is updated
2) Can occur only when block is replaced
Minimizes memory write operations
Leaves main memory in an obsolete state

57. Chapter01 Computer System Overview
1.1 Basic Elements(基本构成)
1.2 Run Instruction(指令执行)
1.3 interrupt(中断)
1.4 structure of storage(存储结构)
1.5 cache(高速缓存)
1.6 I/O(输入/输出)

58. 1.6 I/O Communication Techniques (1/3)
Method1/3: Programmed I/O
I/O module performs the action, not the processor
Sets appropriate bits in the I/O status register
No interrupts occur
Processor checks status until operation is complete

59. 1.6 I/O Communication Techniques (2/3)
Method2/3: Interrupt-Driven I/O
Processor is interrupted when I/O module ready to exchange data
Processor saves context of program executing and begins executing interrupt-handler
No needless waiting
缺点：Consumes a lot of processor time because every word read or written passes through the processor

60. 1.6 I/O Communication Techniques (3/3)
Method3/3: Direct Memory Access
I/O exchanges occur directly with memory
Relieves the processor responsibility for the exchange
Transfers a block of data directly to or from memory 流程
Processor grants I/O module authority to read from or write to memory
An interrupt is sent when the transfer is complete
Processor continues with other work

61. This is the end of this chapter