1. Chip&Core Architecture
Chip Architecture
4 multi-thread processor cores
4 MB L2 cache, multi-bank
None-blocking crossbar switch between cores and L2 cache, scalable from 1 to 4 cores
Directory based L2 cache coherency
      Thread scheduler
FB-DIMM memory controller (possibly)
      Reconfigurable crypto-coprocessor supporting coding and decoding symmetric algorithms (DES, AES, RCx, GDES, TDES, CRYPT,etc)
     
Core Architecture
MIPS ISA;
4 threads, Coarse Multithreading, only one thread at a time;
16 KB L1 instruction cache, 8 KB (or 16KB)  L1 data cache;
5-8 stage pipeline
floating point unit

2. Why Multi-thread core
To reduce the effect of memory access bottleneck: When a thread must wait for memory, just switch to another thread, hide the memory latency problem.
With a lessened effective penalty for memory misses we can make branch prediction less aggressive, which means easier development and a smaller, simpler core.
    We also planned to have a hardware thread scheduler, which can balance overall workload by dispatching threads to appropriate cores. This part will be coupled with commercial OS, as LINUX.
Each MIPS processor will be able to be connected in an efficient manner to the Reconfigurable crypto-coprocessor. This will be done through specific network.

4. Multicore architecture
Control
Computing
TLP et RPU
Reconfigurable Interconnections
Complexity management
Embedded reliability
Energy management
Advanced technologies
Reconfigurable coprocessors OS
Scheduling, …
Switch and interconnection
RISC core
RISC core L2 L2 L1 L1
RISC core
RISC core L1 L1
RISC core
RISC core L1 L1
RPU fg core
RPU cg core L1 L1

5. 1er issue : Parallelism management
L1 cache design :
High performance cache
Full custom cache design
Memory management
Memory hierarchy
Multibank memory
System design
Considering, at the same time, both sw and hw aspects
Embedded thread controller
QoS functionnalities
Shared ressources
Multi-bank L2 cache
Thread Controller
MIPS core
I$/D$ M2

6. 2nd issue : Interconnections
High performance Interconnections networks
Reconfigurable & Dynamic configuration
Asynchronous
Advanced design
I/O management
HW and embedded SW design
Switch and interconnection
I/O
Thread Controller
MIPS core
I$/D$
Multi-bank L2 cache M2

7. 3rd issue : Reconfigurable cryptoprocessor
High performance cryptoprocessor
For high data rate
Symetric cryptography
Multi-mode cryptography
On the fly reconfiguration
Highly interconnected to processor, memory and I/O
Switch and interconnection
Thread Controller
I/O
MIPS core
I$/D$
R. Crypto Coprocessor.
Multi-bank L2 cache M2

8. Parallelism management
Thread Controller
Switch and interconnection OS
R. Crypto Coprocessor.
MIPS core
I$/D$
Multi-bank L2 cache
I/O
3 R&D areas
Parallelism management
Interconnections
Reconfigurable cryptoprocessor