1. Chapter 17 - 18 Hardwired vs Microprogrammed Control Multithreading
Multicore Computers
Summary of Parallel Organizations
Recap of Course
Final Exam: Next Thursday- Same time / same place

2. Hardwired Control (State machine - Combinational Logic)

3. Microprogrammed Control
Micro-Control Memory
Note: Assume we begin in State A
Control Outputs
Next Location
Address C1 C2 C3 C4 C5 C6 C7 C8 C9
C10
TRUE
FALSE 1 4 2 5 3 6 7 8 9 10
Sequencer:
Micro-Control
Memory

4. Definitions of Threads and Processes
An instance of program running on computer
Thread: dispatchable unit of work within process
Includes processor context (which includes the program counter and stack pointer) and data area for stack
Threads execute sequentially, but are Interruptible
the processor can turn to another thread
Thread switch
Switching processor between threads within same process
Typically less costly than process switch

5. Implicit and Explicit Multithreading
Explicit Multithreading is Concurrently executing instructions from different explicit threads
Instructions are Interleaved from different threads on shared pipelines or executed in Parallel on separate pipelines
Implicit multithreading is concurrent execution of multiple threads extracted from a single sequential program
Implicit threads are defined statically by the compiler or dynamically by hardware

6. Scalar Threading

7. Multiple Instruction Issue Threading

8. Parallel Diagram

9. Multicore Organization Alternatives

10. Intel x86 Multicore Organization Core i7
Released November 2008
Speculative pre-fetch for caches
Simultaneous multi-threading (SMT)
4 SMT cores, each supporting 4 threads  appears as 16 cores
On chip DDR3 memory controller
Three 8 byte channels (192 bits) giving 32GB/s
QuickPath Interconnection
Cache coherent point-to-point link
High speed communications between processor chips
6.4G transfers per second, 16 bits per transfer
Total bandwidth 25.6GB/s

11. Intel Core i7 Block Diagram
.3 ns/B !

12. Intel Core i7 approx 45x45 mm 45 nm feature size

13. Parallel Processor Architecture Summary
Very Tightly Coupled Tightly Coupled Moderately Coupled

14. MultiCore Organization (Very tightly Coupled or Single Processor)

15. Symmetric Multiprocessor (SMP) Organization (Tightly Coupled)

16. Non-Uniform Memory Access (NUMA) Organization (Moderately Coupled)

17. Cluster Organization (Loosely Coupled)