Introduction to VHDL for Synthesis

Introduction to VHDL for Synthesis
Lecture 4 Introduction to VHDL for Synthesis Simple Testbenches

Required reading P. Chu, RTL Hardware Design using VHDL
Chapter 2, Overview of Hardware Description Languages Chapter 3, Basic Language Constructs of VHDL

Recommended reading Wikipedia – The Free On-line Encyclopedia
VHDL - Verilog - Accellera -

ECE 448 – FPGA and ASIC Design with VHDL

Brief History of VHDL ECE 448 – FPGA and ASIC Design with VHDL

VHDL VHDL is a language for describing digital hardware used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language 8

Genesis of VHDL State of art circa 1980
Multiple design entry methods and hardware description languages in use No or limited portability of designs between CAD tools from different vendors Objective: shortening the time from a design concept to implementation from 18 months to 6 months The Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is the product of a US Government request for a new means of describing digital hardware. The Very High Speed Integrated Circuit (VHSIC) Program was an initiative of the Defense Department to push the state of the art in VLSI technology, and VHDL was proposed as a versatile hardware description language. 9

A Brief History of VHDL June 1981: Woods Hole Workshop
July 1983: contract awarded to develop VHDL Intermetrics IBM Texas Instruments August 1985: VHDL Version 7.2 released December 1987: VHDL became IEEE Standard and in 1988 an ANSI standard The contract for the first VHDL implementation was awarded to the team of Intermetrics, IBM, and Texas Instruments in July However, development of the language was not a closed process and was subjected to public review throughout the process (accounting for Versions 1 through 7.1). The final version of the language, developed under government contract, was released as VHDL Version 7.2. In March 1986, IEEE proposed a new standard VHDL to extend and modify the language to fix identified problems. In December 1987, VHDL became IEEE Standard VHDL was again modified in September 1993 to further refine the language. These refinements both clarified and enhanced the language. The major changes included much improved file handling and a more consistent syntax and resulted in VHDL Standard 10

Four versions of VHDL Four versions of VHDL: IEEE-1076 1987
IEEE  most commonly supported by CAD tools IEEE (minor changes) IEEE (minor changes) IEEE

ECE 448 – FPGA and ASIC Design with VHDL

Verilog ECE 448 – FPGA and ASIC Design with VHDL

Verilog Simpler and syntactically different C-like
Gateway Design Automation Co., 1985 Gateway acquired by Cadence in 1990 IEEE Standard Early de facto standard for ASIC programming Programming language interface to allow connection to non-Verilog code

VHDL vs. Verilog Government Developed Commercially Developed Ada based
C based Strongly Type Cast Mildly Type Cast Case-insensitive Case-sensitive Difficult to learn Easier to Learn More Powerful Less Powerful

How to learn Verilog by yourself ?

Features of VHDL and Verilog
Technology/vendor independent Portable Reusable

VHDL Fundamentals ECE 448 – FPGA and ASIC Design with VHDL

Naming and Labeling (1) VHDL is case insensitive Example:
Names or labels databus Databus DataBus DATABUS are all equivalent

Naming and Labeling (2) General rules of thumb (according to VHDL-87)
All names should start with an alphabet character (a-z or A-Z) Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.) Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid) All names and labels in a given entity and architecture must be unique

Valid or invalid? 7segment_display A87372477424 Adder/Subtractor
/reset And_or_gate AND__OR__NOT Kogge-Stone-Adder Ripple&Carry_Adder My adder

Extended Identifiers Allowed only in VHDL-93 and higher:
Enclosed in backslashes May contain spaces and consecutive underscores May contain punctuation and reserved characters within a name (!, ?, ., &, +, -, etc.) VHDL keywords allowed Case sensitive Examples: /rdy/ /My design/ /!a/ /RDY/ /my design/ /-a/ ECE 448 – FPGA and ASIC Design with VHDL

Free Format VHDL is a “free format” language
No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then or if (a=b) then if (a = b) then are all equivalent

Readability standards & coding style
Adopt readability standards based on one of the the two main textbooks: Chu or Brown/Vranesic Use coding style recommended in OpenCores Coding Guidelines linked from the course web page Strictly enforced by the lab instructors and myself. Penalty points may be enforced for not following these recommendations!!!

Comments Comments in VHDL are indicated with
a “double dash”, i.e., “--” Comment indicator can be placed anywhere in the line Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block extending over a couple of lines Examples: -- main subcircuit Data_in <= Data_bus; reading data from the input FIFO

Comments Explain Function of Module to Other Designers
Explanatory, Not Just Restatement of Code Locate Close to Code Described Put near executable code, not just in a header

Design Entity ECE 448 – FPGA and ASIC Design with VHDL

Example: NAND Gate a b z 1 a z b

Example VHDL Code 3 sections to a piece of VHDL code
File extension for a VHDL file is .vhd Name of the file should be the same as the entity name (nand_gate.vhd) [OpenCores Coding Guidelines] LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model; LIBRARY DECLARATION ENTITY DECLARATION ARCHITECTURE BODY

Design Entity Design Entity - most basic building block of a design.
entity declaration architecture 1 architecture 2 architecture 3 design entity Design Entity - most basic building block of a design. One entity can have many different architectures.

Entity Declaration Entity Declaration describes the interface of the component, i.e. input and output ports. Entity name Port type Port names Semicolon ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; No Semicolon after last port Reserved words Port modes (data flow directions)

Entity declaration – simplified syntax
ENTITY entity_name IS PORT ( port_name : port_mode signal_type; …………. port_name : port_mode signal_type); END entity_name;

Port Mode IN Port signal Entity a Driver resides outside the entity

Port Mode OUT c <= z z c Entity
Port signal z Output cannot be read within the entity c Driver resides inside the entity c <= z

Port Mode OUT (with extra signal)
Entity Port signal x z c Signal x can be read inside the entity Driver resides inside the entity z <= x c <= x

Port Mode INOUT a Entity Port signal Signal can be
read inside the entity Driver may reside both inside and outside of the entity

Port Modes - Summary The Port Mode of the interface describes the direction in which data travels with respect to the component In: Data comes into this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment. Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment. Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.

Architecture (Architecture body)
Describes an implementation of a design entity Architecture example: ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model;

Architecture – simplified syntax
ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code END architecture_name;

Entity Declaration & Architecture
nand_gate.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow;

Tips & Hints Place each entity in a different file.
The name of each file should be exactly the same as the name of an entity it contains. These rules are not enforced by all tools but are worth following in order to increase readability and portability of your designs

Tips & Hints Place the declaration of each port,
signal, constant, and variable in a separate line These rules are not enforced by all tools but are worth following in order to increase readability and portability of your designs

Libraries ECE 448 – FPGA and ASIC Design with VHDL

Library Declarations Library declaration
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model; Library declaration Use all definitions from the package std_logic_1164

Library declarations - syntax
LIBRARY library_name; USE library_name.package_name.package_parts;

Fundamental parts of a library
PACKAGE 1 PACKAGE 2 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS

Libraries ieee std work Need to be explicitly declared
Specifies multi-level logic system, including STD_LOGIC, and STD_LOGIC_VECTOR data types Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc. Visible by default Holds current designs after compilation

STD_LOGIC Demystified
ECE 448 – FPGA and ASIC Design with VHDL

What is STD_LOGIC you ask?
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow; What is STD_LOGIC you ask?

BIT versus STD_LOGIC BIT type can only have a value of ‘0’ or ‘1’
STD_LOGIC can have nine values ’U’,’X’,‘0’,’1’,’Z’,’W’,’L’,’H’,’-’ Useful mainly for simulation ‘0’,’1’, and ‘Z’ are synthesizable (your codes should contain only these three values)

STD_LOGIC type demystified
Value Meaning ‘U’ Uninitialized ‘X’ Forcing (Strong driven) Unknown ‘0’ Forcing (Strong driven) 0 ‘1’ Forcing (Strong driven) 1 ‘Z’ High Impedance ‘W’ Weak (Weakly driven) Unknown ‘L’ Weak (Weakly driven) 0. Models a pull down. ‘H’ Weak (Weakly driven) 1. Models a pull up. ‘-’ Don't Care Signals are used to connect different parts of a design. They can be thought of as “wire” in conventional sense. Every signal has a type. A type is all the valid values that a signal can assume. VHDL naturally supports bit type, which allows signals of this (bit) type to take the values ‘0’ or ‘1’. Signals of type integer can take integer values between +(231 – 1) to -(231-1). Wire in real implementation may need to take an unknown value, ‘X’ or high impedance value, ‘Z’. Thus, IEEE 1164 standard defined std_logic with nine values listed in Table 1. Std_logic_vector is an array or vector of std_logic type. It represents a bus and has dimension associated with it, which is known as the range of vector.

More on STD_LOGIC Meanings (1)
‘1’ ‘X’ Contention on the bus X ‘0’

VDD VDD ‘H’ ‘0’ ‘1’ ‘L’

Do not care. Can be assigned to outputs for the case of invalid inputs(may produce significant improvement in resource utilization after synthesis). Must be used with great caution. For example in VHDL, the comparison ’1’ = ’-’ gives FALSE. ‘-’

Resolving logic levels
U X Z W L H - U U U U U U U U U U X U X X X X X X X X 0 U X X X 1 U X X X Z U X Z W L H X W U X W W W W X L U X L W L W X H U X H W W H X - U X X X X X X X X

STD_LOGIC Rules In ECE 545 use std_logic or std_logic_vector for all entity input or output ports Do not use integer, unsigned, signed, bit for ports You can use them inside of architectures if desired You can use them in generics Instead use std_logic_vector and a conversion function inside of your architecture [Consistent with OpenCores Coding Guidelines]

Modeling Wires and Buses

Signals a b SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); a 1 wire b bus 8

Standard Logic Vectors
SIGNAL a: STD_LOGIC; SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0); ………. a <= ‘1’; b <= ”0000”; Binary base assumed by default c <= B”0000”; Binary base explicitly specified d <= X”AF67”; Hexadecimal base e <= O”723”; Octal base

Vectors and Concatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0); a <= ”0000”; b <= ”1111”; c <= a & b; c = ” ” d <= ‘0’ & ” ”; -- d <= ” ” e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- e <= ” ”

Fixed Rotation in VHDL A<<<1 ArotL <=
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0); A(3) A(2) A(1) A(0) A<<<1 Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required. A(2) A(1) A(0) A(3) ArotL <=

Fixed Shift in VHDL A>>1 AshiftR <=
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0); A(3) A(2) A(1) A(0) A>>1 Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required. ‘0’ A(3) A(2) A(1) AshiftR <=

VHDL Design Styles ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles VHDL Design Styles behavioral dataflow structural
Testbenches dataflow behavioral (sequential) structural Concurrent statements Components and interconnects Sequential statements Registers State machines Decoders Subset most suitable for synthesis

xor3 Example

Entity xor3_gate LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY xor3_gate IS PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC ); end xor3_gate;

Dataflow Architecture (xor3_gate)
ARCHITECTURE dataflow OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC; BEGIN U1_OUT <= A XOR B; Result <= U1_OUT XOR C; END dataflow; U1_OUT

Dataflow Description Describes how data moves through the system and the various processing steps. Dataflow uses series of concurrent statements to realize logic. Dataflow is the most useful style to describe combinational logic Dataflow code also called “concurrent” code Concurrent statements are evaluated at the same time; thus, the order of these statements doesn’t matter This is not true for sequential/behavioral statements This order… U1_out <= A XOR B; Result <= U1_out XOR C; Is the same as this order…

Structural Architecture in VHDL 87
ARCHITECTURE structural OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC; COMPONENT xor2 PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: xor2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: xor2 PORT MAP (I1 => U1_OUT, I2 => C, Y => Result); END structural; A B C Result xor3_gate U1_OUT I1 I2 Y I1 I2 Y PORT NAME LOCAL WIRE NAME

xor2 xor2.vhd LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC); END xor2; ARCHITECTURE dataflow OF xor2 IS BEGIN Y <= I1 xor I2; END dataflow;

Structural Architecture in VHDL 93
ARCHITECTURE structural OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC; BEGIN U1: entity work.xor2(dataflow) PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: entity work.xor2(dataflow) PORT MAP (I1 => U1_OUT, I2 => C, Y => Result); END structural; A B C Result xor3_gate U1_OUT I1 I2 Y I1 I2 Y PORT NAME LOCAL WIRE NAME

Structural Description
Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components. Structural style is useful when expressing a design that is naturally composed of sub-blocks.

Behavioral Architecture (xor3 gate)
ARCHITECTURE behavioral OF xor3 IS BEGIN xor3_behave: PROCESS (A, B, C) IF ((A XOR B XOR C) = '1') THEN Result <= '1'; ELSE Result <= '0'; END IF; END PROCESS xor3_behave; END behavioral;

Behavioral Description
It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works). This style uses PROCESS statements in VHDL.

Testbenches ECE 448 – FPGA and ASIC Design with VHDL

Testbench Defined Testbench = VHDL entity that applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs. The results can be viewed in a waveform window or written to a file. Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability). The same Testbench can be easily adapted to test different implementations (i.e. different architectures) of the same design.

Design Under Test (DUT)
Simple Testbench Processes Generating Stimuli Design Under Test (DUT) Verify simulated outputs with expected output to see if the design behaves according to specification Observed Outputs

Possible sources of expected results used for comparison
Testbench actual results VHDL Design = ? Representative Inputs Manual Calculations or Reference Software Implementation (C, Java, Matlab ) expected results

Testbench The same testbench can be used to
test multiple implementations of the same circuit (multiple architectures) testbench design entity Architecture 1 Architecture 2 Architecture N

Testbench Anatomy ENTITY my_entity_tb IS --TB entity has no ports
END my_entity_tb; ARCHITECTURE behavioral OF tb IS --Local signals and constants COMPONENT TestComp --All Design Under Test component declarations PORT ( ); END COMPONENT; BEGIN DUT:TestComp PORT MAP( Instantiations of DUTs ); testSequence: PROCESS -- Input stimuli END PROCESS; END behavioral; Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required.

Testbench for XOR3 (1) LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY xor3_tb IS END xor3_tb; ARCHITECTURE behavioral OF xor3_tb IS -- Component declaration of the tested unit COMPONENT xor3 PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC ); END COMPONENT; -- Stimulus signals - signals mapped to the input and inout ports of tested entity SIGNAL test_vector: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL test_result : STD_LOGIC;

Testbench for XOR3 (2) BEGIN UUT : xor3 PORT MAP (
A => test_vector(2), B => test_vector(1), C => test_vector(0), Result => test_result); ); Testing: PROCESS test_vector <= "000"; WAIT FOR 10 ns; test_vector <= "001"; test_vector <= "010"; test_vector <= "011"; test_vector <= "100"; test_vector <= "101"; test_vector <= "110"; test_vector <= "111"; END PROCESS; END behavioral;

VHDL Design Styles Concurrent statements Components and interconnects
dataflow structural behavioral Concurrent statements Components and interconnects Sequential statements Testbenches

Process without Sensitivity List and its use in Testbenches

What is a PROCESS? A process is a sequence of instructions referred to as sequential statements. The keyword PROCESS A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS. Testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; test_vector<=“10”; test_vector<=“11”; END PROCESS;

Execution of statements in a PROCESS
Testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; test_vector<=“10”; test_vector<=“11”; END PROCESS; The execution of statements continues sequentially till the last statement in the process. After execution of the last statement, the control is again passed to the beginning of the process. Order of execution Program control is passed to the first statement after BEGIN

PROCESS with a WAIT Statement
The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns. This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated. Testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; test_vector<=“10”; test_vector<=“11”; WAIT; END PROCESS; Order of execution Program execution stops here

WAIT FOR vs. WAIT WAIT FOR: waveform will keep repeating itself forever … 1 2 3 1 2 3 WAIT : waveform will keep its state after the last wait instruction. …

Specifying time in VHDL

Time values (physical literals) - Examples
7 ns 1 min min 10.65 us 10.65 fs unit of time most commonly used in simulation Numeric value Space (required) Unit of time

Units of time Unit Definition Base Unit
fs femtoseconds (10-15 seconds) Derived Units ps picoseconds (10-12 seconds) ns nanoseconds (10-9 seconds) us microseconds (10-6 seconds) ms miliseconds (10-3 seconds) sec seconds min minutes (60 seconds) hr hours (3600 seconds)

Simple Testbenches ECE 448 – FPGA and ASIC Design with VHDL

Generating selected values of one input
SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0); BEGIN testing: PROCESS test_vector <= "000"; WAIT FOR 10 ns; test_vector <= "001"; test_vector <= "010"; test_vector <= "011"; test_vector <= "100"; END PROCESS; END behavioral;

Generating all values of one input
SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000"; BEGIN testing: PROCESS WAIT FOR 10 ns; test_vector <= test_vector + 1; end process TESTING; END behavioral;

Arithmetic Operators in VHDL (1)
To use basic arithmetic operations involving std_logic_vectors you need to include the following library packages: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; or USE ieee.std_logic_signed.all; Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required.

Arithmetic Operators in VHDL (2)
You can use standard +, - operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C <= A + B; Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required.

Different ways of performing the same operation
signal count: std_logic_vector(7 downto 0); You can use: count <= count + “ ”; or count <= count + 1; count <= count + ‘1’;

Different declarations for the same operator
Declarations in the package ieee.std_logic_unsigned: function “+” ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector; function “+” ( L: std_logic_vector; R: integer) return std_logic_vector; function “+” ( L: std_logic_vector; R:std_logic) return std_logic_vector;

Operator overloading Operator overloading allows different argument types for a given operation (function) The VHDL tools resolve which of these functions to select based on the types of the inputs This selection is transparent to the user as long as the function has been defined for the given argument types.

Generating all possible values of two inputs
SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0); SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0); BEGIN double_loop: PROCESS test_ab <="00"; test_sel <="00"; for I in 0 to 3 loop for J in 0 to 3 loop wait for 10 ns; test_ab <= test_ab + 1; end loop; test_sel <= test_sel + 1; END PROCESS; END behavioral;

Generating periodical signals, such as clocks
CONSTANT clk1_period : TIME := 20 ns; CONSTANT clk2_period : TIME := 200 ns; SIGNAL clk1 : STD_LOGIC; SIGNAL clk2 : STD_LOGIC := ‘0’; BEGIN clk1_generator: PROCESS clk1 <= ‘0’; WAIT FOR clk1_period/2; clk1 <= ‘1’; END PROCESS; clk2 <= not clk2 after clk2_period/2; END behavioral;

Generating one-time signals, such as resets
CONSTANT reset1_width : TIME := 100 ns; CONSTANT reset2_width : TIME := 150 ns; SIGNAL reset1 : STD_LOGIC; SIGNAL reset2 : STD_LOGIC := ‘1’; BEGIN reset1_generator: PROCESS reset1 <= ‘1’; WAIT FOR reset1_width; reset1 <= ‘0’; WAIT; END PROCESS; reset2_generator: PROCESS WAIT FOR reset2_width; reset2 <= ‘0’; END behavioral;

Typical error SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL reset : STD_LOGIC; BEGIN generator1: PROCESS reset <= ‘1’; WAIT FOR 100 ns reset <= ‘0’; test_vector <="000"; WAIT; END PROCESS; generator2: PROCESS WAIT FOR 200 ns test_vector <="001"; WAIT FOR 600 ns test_vector <="011"; END behavioral;

Introduction to VHDL for Synthesis

Similar presentations

Presentation on theme: "Introduction to VHDL for Synthesis"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Introduction to VHDL for Synthesis

Similar presentations

Presentation on theme: "Introduction to VHDL for Synthesis"— Presentation transcript:

Similar presentations

About project

Feedback