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Hardware Trojan Detection
Jonathan Frey Advisor: Qiaoyan Yu
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Overview Problem Definition Design Objectives Design Flow
Design Diagram Implementation and Testing Goals Budget Timeline
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Problem Definition Outsourcing of IC manufacturing process
Protection against malicious hardware inclusions Hardware Trojan (HT) Detection and Protection module Show importance of the detection and protection against HTs
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Design Objectives Be able to detect and protect against HTs
Timing between modules must be flawless Cannot introduce too large of an overhead Visually show design works via FPGA
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Design Flow Diagram DeECC Module ECC DeECC Wire Isolation
Bit Permutation Syndrome Calculation Bit De-Permutation No error, continue DeECC Error? Yes, error present Not same error, change current key Key Management Module Same error? Store current data with error Compare current data with previous data Same error, change current key, and activate wire isolation Wire Isolation
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ECC/DeECC modules Error Control Coding
Modules used to compare current bits in ECC and DeECC Use extra bits to calculate syndrome Syndrome can tell if error is present
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Permutation Modules Creates controllable bit mixing on interconnects
If HT exists on interconnects, permutation of bits may deactivate HT Permutation patterns control how bits are mixed Key controls which permutation pattern is currently used
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Key Management Module Key controls bit mixing pattern for Permutation and DePermutation modules Different keys will mix bits in different ways Key will change when error is found
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Wire Isolation Biggest challenge so far Most difficult to implement
Isolates/won’t use current wire with error 1) Reroute error wire 2) Send bit through a non- error wire
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Implementation and Testing
Implement first using Verilog HDL Already have Verilog code for 32bit/38bit ECC and DeECC Modules Have already implemented HTs in Verilog within ECC Module Once verified in Verilog, hope to synthesize to FPGA board
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Goals Implement design using Verilog HDL
Successfully synthesize working Verilog design to FPGA board Use external control (keyboard) to activate present HT, to show importance of detecting and protecting against HTs
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Budget Estimate
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2013 2014 Project Timeline Aug Sept Oct Nov Dec Jan Feb March April
May Research and work on project idea Finalize idea Finalize circuits Code in Verilog Verifcation and Testing of Design FPGA work External control Proposal Progress Report URC Poster Print Poster URC Final Report
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