1. Presented by Mohsen Shakiba
Receiver implementation considerations & techniques Experimental Results
Presented by
Mohsen Shakiba

2. Outline Modulation & Demodulation techniques
- Digital PLL Design Considerations
- Experimental results on a full digital FM receiver design on FPGA

3. Modulation & Demodulation techniques ( Introduction )
A basic communication system transmits and receives information over a carrier frequency ( )
This carrier can be modulated in Amplitude , Frequency or Phase
The modulations are called ASK , FSK & PSK in order

4. Modulation & Demodulation techniques ( Sample Modulated Signal )

5. Modulation & Demodulation techniques ( Demodulators Classification )
A coherent receiver must recover the unknown carrier phase ( ). While an incoherent receiver does not need to do so .
Demodulators
Incoherent
Coherent
Envelope detector ( only AM )
Limiter discriminator ( only FM )
Quadrature mixer
Quadrature sampler
Hilbert transformer
Hilbert sampler
Phase-locked loop ( PLL )
Costas loop (CL)

6. Digital PLL Design Considerations ( Digital PLL scheme )
PLL is thus a frequency synthesizer that keeps itself synchronized with a reference signal.
Input signal : x[n] = a cos(2π fcnTs + θ[n]) + ν[n]
Output signal : y[n] = b cos(2π fcnTs + φ[n])

7. Digital PLL Design Considerations ( Digital PLL scheme )
€[n], is an estimate of the phase difference θ[n] − φ[n]
The control signal c[n] : φ[n + 1] = φ[n] + µc[n]
µ is a constant, called step-size parameter.
we assume that Ts is small and let µ = Tc

8. Digital PLL Design Considerations ( Linear Model of PLL )
Z transform

9. Digital PLL Design Considerations ( Linear Model of PLL )
the phase transfer function of the discrete-time PLL is :
The same transfer function relates φv [n] and φ[n]

10. Digital PLL Design Considerations ( Linear Model of PLL )
ignoring φ[n], the z-transform of the phase error €[n] is :
So we obtain the phase error transfer function as :

11. Digital PLL Design Considerations ( First order PLL )
A first-order PLL is obtained when : , ,
the condition for the PLL not to drop out of its lock range is | € ss| < π so we have
µ = Ts

12. Digital PLL Design Considerations ( First order PLL MATLAB Simulation)

13. Digital PLL Design Considerations ( First order PLL MATLAB Simulation)
First order PLL tracks a step theta change without any error

14. Digital PLL Design Considerations ( First order PLL MATLAB Simulation )
First order PLL (∆f = 1) tracks a linear theta change with a steady state error less than π

15. Digital PLL Design Considerations ( Second order PLL )
A Second-order PLL is obtained when : ,
the steady-state error of the second-order discrete-time PLL will approach zero only when β = −1

16. Digital PLL Design Considerations ( Second order PLL MATLAB Simulation)

17. Digital PLL Design Considerations ( Second order PLL MATLAB Simulation )
Second order PLL tracks a step theta change without any error

18. Digital PLL Design Considerations ( Second order PLL MATLAB Simulation )
Second order PLL tracks a step theta change without any error for β = −1

19. Experimental results for a full digital FM receiver design ( Work Description )
FM Modulated Signal Specifications
Software Works in MATLAB
Simulation the behavior of an analog PLL for FM Demodulation
- Simulation the behavior of target digital PLL for FM Demodulation
A MATLAB Test-bench for analyzing the Hardware implementation
Hardware Works on FPGA
Post Place & Route implementation of a full digital FM demodulator on
a Xilinx spartan3 xc3s400 IC
- Improve the results in speed adjunction and area reduction up to 100%
- writing an integrated test-bench with MATLAB and Modelsim simulator

20. Experimental results for a full digital FM receiver design ( Overall Design Scheme )

21. Experimental results for a full digital FM receiver design ( Loop Filter Unit )

22. Experimental results for a full digital FM receiver design ( NCO Unit )

23. Experimental results for a full digital FM receiver design ( Low Pass Filter Unit )

24. Experimental results for a full digital FM receiver design ( Detailed Design Scheme )

25. Experimental results for a full digital FM receiver design ( Pulse Test Signal )

26. Experimental results for a full digital FM receiver design ( Triangle Test Signal )

27. Experimental results for a full digital FM receiver design ( MATLAB simulation results for software PLL )
Comparison between original signal and demodulated version in MATLAB Model for PLL

28. Experimental results for a full digital FM receiver design ( MATLAB simulation results for software PLL )
Comparison between original signal and demodulated version in MATLAB Model for PLL

29. Experimental results for a full digital FM receiver design ( MATLAB simulation results for software PLL )
Comparison between original signal and demodulated version in MATLAB Model for PLL

30. Experimental results for a full digital FM receiver design ( MATLAB simulation results for software PLL )
Comparison between original signal and demodulated version in MATLAB Model for PLL

31. Experimental results for a full digital FM receiver design ( PLL Hardware Post Place & Route implementation on FPGA )
Design implemented on a xilinx spartan xc3s400 with clock frequency 50 MHz

32. Device utilization summary:
Experimental results for a full digital FM receiver design ( Post synthesis Results )
Device utilization summary:
Selected Device : 3s400ft256-4
Number of Slices: out of %
Number of Slice Flip Flops: out of %
Number of 4 input LUTs: out of %
Number of bonded IOBs: out of %
Number of GCLKs: out of %
===========================================
TIMING REPORT
Clock Information:
Clock Signal | Clock buffer(FF name) | Load |
CLK | BUFGP | |
Timing Summary:
Speed Grade: -4
Minimum period: ns (Maximum Frequency: MHz)
Minimum input arrival time before clock: 6.584ns
Maximum output required time after clock: 7.241ns
Maximum combinational path delay: No path found
Device utilization summary:
Selected Device : 3s400ft256-4
Number of Slices: out of %
Number of Slice Flip Flops: out of %
Number of 4 input LUTs: out of %
Number of bonded IOBs: out of %
Number of GCLKs: out of %
============================================
TIMING REPORT
Clock Information:
Clock Signal | Clock buffer(FF name) | Load |
CLK | BUFGP | |
Timing Summary:
Speed Grade: -4
Minimum period: ns (Maximum Frequency: MHz)
Minimum input arrival time before clock: ns
Maximum output required time after clock: 7.165ns
Maximum combinational path delay: No path found

33. Experimental results for a full digital FM receiver design ( Post Place & Route Results )

34. Experimental results for a full digital FM receiver design ( Post Place & Route Results in ModelSim )
Design implemented on a xilinx spartan xc3s400 with clock frequency 50 MHz

35. Experimental results for a full digital FM receiver design ( Post Place & Route Results in ModelSim )
Design implemented on a xilinx spartan xc3s400 with clock frequency 50 MHz

36. Modulation Demodulation Unit Unit Analyzer MATLAB Input Output File
Experimental results for a full digital FM receiver design ( Hardware System Test Scenario )
Modulation
Unit
Demodulation
Unit
Analyzer
MATLAB
FPGA Design
Test Bench
Input
File
Output
File
Analysis Path

37. The distance between them is 5.94
Experimental results for a full digital FM receiver design ( Hardware output analysis in MATLAB )
Comparasion between original signal and demodulated version in ideal signal transmition
The distance between them is 5.94

38. The distance between them is 8.04
Experimental results for a full digital FM receiver design ( Hardware output analysis in MATLAB )
Comparasion between original signal and demodulated version in SNR = 50 dB
The distance between them is 8.04

39. The distance between them is 14.86
Experimental results for a full digital FM receiver design ( Hardware output analysis in MATLAB )
Comparasion between original signal and demodulated version in SNR = 20 dB
The distance between them is 14.86

40. one man say’s “the discreet”
Experimental results for a full digital FM receiver design ( Software PLL simulation in MATLAB for Audio test)
one man say’s “the discreet”

41. one man say’s “the discreet”
Experimental results for a full digital FM receiver design ( Hardware Audio test in Modelsim)
one man say’s “the discreet”

42. one man say’s “the discreet”
Experimental results for a full digital FM receiver design ( Hardware output analysis in MATLAB for Audio test)
one man say’s “the discreet”

43. Modulation Demodulation Unit Unit MATLAB Input Output File File
Experimental results for a full digital FM receiver design ( Future work on System Test Scenario )
Modulation
Unit
Demodulation
Unit
MATLAB
FPGA Design
Test Bench
Input
File
Output
File

44. MATLAB Server Response Request
Experimental results for a full digital FM receiver design ( Future work on System Test Scenario )
MATLAB
Server
Response
Request

45. References Digital and Analog communication systems – K.SAM Shanmugam
Digital signal processing with FPGA – Uwe Meyer-Baese
Signal Processing Techniques for Software Radio - Behrouz Farhang

46. Thanks for your attention