1. Electronic Design Laboratory
CD4007 CMOS Pairs
Electronic Design Laboratory

2. Overview CD4007 Dual Complementary Pair Plus Inverter
Rise Time and Fall Time
Design Number Documents
Six Configurations

3. CD4007

4. CD4007
Reference
Inverter
and
Center
Pair

5. Warnings Don’t subject CD4007 to high voltages or static electricity.
Store CD4007 in an anti-static bag or in anti-static foam.
Momentarily touch a metal part of the workbench to discharge yourself before handling the part or touching the leads.
Never let voltage on any pin be more positive than pin 14 or more negative than pin 7. The circuit may “latch up”— possibly causing permanent damage.

6. Warnings
Always connect pin 7 (substrate for n-channel transistors) to your negative supply voltage and pin 14 (substrate for p-channel transistors) to your positive supply voltage.
Connect or turn-on the supply voltages (pins 7 & 14) before any other voltages in your circuit.
For added safety, ground any unused inputs.

7. Standard Load -- Pin 12
47 pF

8. Rise & Fall Time
VOUT
100%
90%
10% 0%
Rise
Fall
time

9. Rise Time VDD PLH = 1.29 RonpC r = 2 PLH Ronp r = 2.58 RonpC 47 pF
VC(0) = 0 V

10. Fall Time VC(0) = 5 V PHL = 1.29 RonnC f = 2 PHL 47 pF
f = 2.58 RonnC
47 pF
Ronn

11. Design Number Document

12. Design Number Document

13. Design Number Document
1SP
1DP
1A DN
1SN
VDD
2A DP
2DN
VSS
3SP
3A Y
3SN 2 1 5 4 14 13 8 7 11 12 9 3 6 10

14. 2-Input NAND RISE and FALL
VDD
Worst-Case One Pull up Ronp for RISE
Worst-Case Two Pull up Ronn
for Fall

15. Six Configurations
Inverter
Triple Inverter

16. Six Configurations
3-Input NAND
3-Input NOR

17. Six Configurations
OR-AND-INVERT (OAI)
OUT = (A+B)•C
1Y = (1A+3A)•2A

18. Six Configurations
Dual Bi-Directional Transmission Gate