1. A NEW 5-TRANSISTOR XOR-XNOR CIRCUIT BASED ON THE PASS TRANSISTOR LOGIC
Vimal Kant Pandey

2. Introduction
XOR-XNOR circuits are the basic building block of many arithmetic and encryption circuits e.g. adders, multipliers, Comparators, Parity Checkers etc.
Careful design and analysis is required for XOR-XNOR circuits to obtained –full output voltage swing, lesser power consumption and delay in the critical path.
We proposed a new XOR-XNOR circuit and compare it’s performance with different designs.
The designs are simulated using TSPICE in the voltage range of 0.6V to 1.2V using 90nm CMOS technology.

3. Previous Work
In the past two decades, a number of circuit techniques have been reported with a view to improve the circuit performance of XOR-XNOR gates [3]-[4].
Shiv et al. [5], the XOR–XNOR circuit is design based on pass-transistor logic (PTL) and CMOS inverter (Fig1 ) has
lower PDP,
less power dissipation and
faster compared to design in [6]
with a low supply voltage.
However both of the circuits give a poor signal output voltage in certain input combination.
Figure1: XOR-XNOR gate using transistors in [5]

4. a full output voltage swing better driving capability
D. Radhakrishnan et al. [2], the XOR and XNOR circuit based on Pass Transistor Logic (PTL) using 6 transistors is reported as shown in Figure 2. It has
a full output voltage swing
better driving capability
Elgamel et al. [7] , has designed improved version of [2] in Fig. 3 has
has better power-delay product and
higher noise immunity .
Figure 3: XOR-XNOR gate using 8 transistors in [4]
Figure 2: XOR-XNOR gate using 6 transistors in [2]

5. Proposed Design
The proposed design of XOR-XNOR gate and it’s operation is shown below: A B M1 M2 M3 M4 M5
XOR
XNOR ON
OFF 1

6. Output Waveform

7. Comparison Table V(v) Proposed 8T[5] 8T[4] 6[2] (5T) Delay .6 .402
.513
.592
.474
for .8
.512
.504
.459
XOR 1
.440
.502
.550
.442
(ns)
1.2
.431
.472
.525
.452
.392
.523
.462
.421
.390
.495
.470
.439
XNOR
.490
.370
.483
.451
Average
1.6
5.29
3.3
power
3.41
10.30
6.8
6.81
XOR-
6.42
18.73
12.62
12.81
11.57
32.91
23.09
(fw)
PDP for
.643
2.17
1.62
1.56
1.371
5.27
3.42
3.12
(YJ)
2.82
9.40
6.94
5.66
4.98
15.06
12.12
10.43
.627
2.76
1.52
1.38
1.32
5.09
3.19
2.98
2.51
9.17
5.70
5.91
4.28
15.89
10.41
10.15

8. References
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M.A. Elgamel, S. Goel, and M.A. Bayoumi, “Noise tolerant low voltage XOR-XNOR for fast arithmetic,” in Proc. Great Lake Symp. VLSI, Washington DC, Apr , 2003, pp
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9. S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y
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