1. THUMB INSTRUCTION SET

2. Objectives
To understand 16-bit Thumb state operation of ARM Processor.
To understand the features of Thumb state operation and how Thumb instructions decompress to ARM Mode.
To know the technique of switching between ARM and Thumb mode of operations.
To know the similarities and differences between ARM and Thumb mode of operation
To understand exception handling and branching in Thumb mode.
To understand operation of data processing instructions and data transfer instructions in Thumb mode.

3. CPU Instruction Set ARM7TDMI processor has two instruction sets:
the standard 32-bit ARM instruction set
a 16-bit THUMB instruction set.

4. Processor Operating States
ARM state
which executes 32-bit, word-aligned ARM instructions.
THUMB state
which operates with 16-bit, halfword-aligned THUMB instructions.

5. Thumb Instruction Set
ARM architecture versions v4T and above define a 16-bit instruction set called the Thumb instruction set. The functionality of the Thumb instruction set is a subset of the functionality of the 32-bit ARM instruction set.
A processor that is executing Thumb instructions is operating in Thumb state. A processor that is executing ARM instructions is operating in ARM state.

6. Thumb Instruction Set
A processor in ARM state cannot execute Thumb instructions, and a processor in Thumb state cannot execute ARM instructions. You must ensure that the processor never receives instructions of the wrong instruction set for the current state.
Each instruction set includes instructions to change processor state.
Note: ARM processors always start executing code in ARM state.

10. Thumb state entry

13. BX and BLX

14. Eg
T=1 on seeing last bit as 1 and ignore last bit and use remaining bits in BX instruction
ADR ARM pseudo-instruction
Load a program-relative or register-relative address into a register.

15.  CODE32 instructs the assembler to interpret subsequent instructions as ARM instructions
CODE16 instructs the assembler to interpret subsequent instructions as THUMB instructions

16. Example

18. Binary Encoding

21. Thumb Programming Model

32. Conti.
All the data processing instructions that operate with and on the 'Lo' registers update the condition code bits (the S bit is set in the equivalent ARM instruction).
The instructions that operate with and on the 'Hi' registers do not change the condition code bits, with the exception of CMP which only changes the condition codes.
The instructions that are requiring '1 or 2 Hi regs' must have one or both register operands specified in the 'Hi' register area.
3, 7 and 8-bit immediate fields is possible depending upon the instructions.
Shift amount for shifting instruction is 5 bit.

37. The following instructions perform ALU operations on to Lo register pair.
All instructions in this group set the CPSR condition codes.

38. Instructions with high register range only cmp sets CC

40. load sign-extended byte/halfword

47. Conditional Branch

50. Egs